參數(shù)資料
型號(hào)： SL28EB717ALIT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 17/22頁(yè)
文件大?。?/td> 0K
描述： IC CLK CK505 TNLCRK/TOPCLF 48QFN
標(biāo)準(zhǔn)包裝： 2,500
系列： EProClock®
類(lèi)型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： Intel CPU 服務(wù)器
輸入： 時(shí)鐘，晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:13
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 166.67MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
SL28EB717
DOC#: SP-AP-0755 (Rev. AA)
Page 4 of 22
Frequency Select Pin FS
Apply the appropriate logic levels to FS inputs before
CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CKPWRGD
and indicates that VTT voltage is stable then FS input values
are sampled. This process employs a one-shot functionality
and once the CKPWRGD sampled a valid HIGH, all other FS,
and CKPWRGD transitions are ignored except in test mode.
Wake-On-LAN (WOL) Support
When power is applied to the VDD_SUSPEND pin, the 25MHz
reference clock output will be enabled under all conditions,
unless the WOL_EN bit, Byte 1 bit 1, is set to “0”. When the
WOL_EN bit Byte 1 bit 1, is set to “0”, the WOL_STP# pin will
function as a PD# pin. By default, the WOL_EN bit is enabled
and set to a “1”. The clock device will support “out-of-the-box”
WOL or after a power outage by enabling the 25MHz reference
clock output when the clock device powers up for the very first
time with only power applied to the VDD_SUSPEND pin and
all other VDD pins power have not been applied.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
1
0
1
0
83.33
100.00
75.00
33.33
1
0
1
83.33
100.00
75.00
33.33
1
0
133.33
100.00
75.00
33.33
1
0
1
133.33
100.00
75.00
33.33
1
0
166.67
100.00
75.00
33.33
1
166.67
100.00
75.00
33.33
Frequency Select Pin (FS)
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1Start
1
Start
8:2
Slave address–7 bits
8:2
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code–8 bits
18:11
Command Code–8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Byte Count–8 bits
20
Repeat start
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SL28EB733ALI 制造商:Silicon Laboratories Inc 功能描述:4 OUTPUT PCI EXPRESS (PCIE) GEN1/2 WITH 25MHZ AND 33MHZ LVCM - Bulk 制造商:Silicon Laboratories Inc 功能描述:IC EMB CLOCK GENERATOR 32QFN
SL28EB733ALIT 制造商:Silicon Laboratories Inc 功能描述:4 OUTPUT PCI EXPRESS (PCIE) GEN1/2 WITH 25MHZ AND 33MHZ LVCM - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC EMB CLOCK GENERATOR 32QFN
SL28EB740AZI 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Tunnel Creek Queen’s Bay platform RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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