EProClock Programmable Technology
參數(shù)資料
型號: SL28EB717ALIT
廠商: Silicon Laboratories Inc
文件頁數(shù): 16/22頁
文件大?。?/td> 0K
描述: IC CLK CK505 TNLCRK/TOPCLF 48QFN
標(biāo)準(zhǔn)包裝: 2,500
系列: EProClock®
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 時鐘,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:13
差分 - 輸入:輸出: 無/是
頻率 - 最大: 166.67MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
SL28EB717
DOC#: SP-AP-0755 (Rev. AA)
Page 3 of 22
EProClock Programmable Technology
EProClock is the world’s first non-volatile programmable
clock. The EProClock technology allows board designer to
promptly achieve optimum compliance and clock signal
integrity; historically, attainable typically through device and/or
board redesigns.
EProClock technology can be configured through SMBus or
hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
- Program Internal or External series resistor on single-ended
clocks
- Program different spread profiles
- Program different spread modulation rate
32
GND_SRC
GND
Ground for SRC clocks
33
VDD_SRC
PWR
3.3V Power supply for SRC clocks
34
VDD_SRC
PWR
3.3V Power supply for SRC clocks
35
SRC6# / CPU2#_ITP
O, DIF Selectable complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC6
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
36
SRC6 / CPU2_ITP,
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC6
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
37
CPU1#
O, DIF Complement differential CPU clock output
38
CPU1
O, DIF True differential CPU clock output
39
VDD_CPU
PWR
3.3V Power supply for CPU clocks
40
CPU0#
O, DIF Complement differential CPU clock output
41
CPU0
O, DIF True differential CPU clock output
42
GND_CPU
GND
Ground for clocks
43
SCLK
I
SMBus compatible SCLOCK
44
SDATA
I/O
SMBus compatible SDATA
45
CPU_STP#*
I, PU
3.3V-tolerant input for stopping CPU outputs (internal 100K-ohm pull-up)
46
PCI/SRC_STP#*
I, PU
3.3V-tolerant input for stopping PCI and SRC outputs (internal 100K-ohm pull-up)
47
XOUT
O
25.00MHz Crystal output, Float XOUT if using only CLKIN (Clock input)
48
XIN / CLKIN
I
25.00MHz Crystal input or 3.3V, 25MHz Clock Input
Pin No.
Name
Type
Description
Frequency Select Pin (FS)
SEL_SATA
FSC
FSB
FSA
CPU
SRC
SATA75/SRC0
PCI
0
100.00
33.33
0
1
100.00
33.33
0
1
0
83.33
100.00
33.33
0
1
83.33
100.00
33.33
0
1
0
133.33
100.00
33.33
0
1
0
1
133.33
100.00
33.33
0
1
0
166.67
100.00
33.33
0
1
166.67
100.00
33.33
1
0
100.00
75.00
33.33
1
0
1
100.00
75.00
33.33
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