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參數(shù)資料
| 型號(hào)： | SL28EB717ALIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK CK505 TNLCRK/TOPCLF 48QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | EProClock® |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:13 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 166.67MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
SL28EB717
DOC#: SP-AP-0755 (Rev. AA)
Page 12 of 22
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the
clock
resumes.
The
maximum
latency
from
the
deassertion to active outputs is no more than two CPU clock
cycles.
PCI/SRC_STP# Assertion
The PCI/SRC_STP# signal is an active LOW input used for
synchronously stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI/SRC_STP# going LOW is 10 ns (tSU).
(See Figure 6.) The PCIF and SRC clocks are affected by this
pin if their corresponding control bit in the SMBus register is
set to allow them to be free running. For SRC clocks assertion
description, please refer to CPU_STP# description.
.
CPU_STP#
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
Tdrive_CPU_STP#,10 ns>200 mV
CPUC Internal
Figure 5. CPU_STP# Deassertion Waveform
Tsu
PC I_STP#
PC I_F
PC I
S RC 100M Hz
Figure 6. PCI_STP# Assertion Waveform
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL28EB719AZI | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Tunnel Creek Queen’s Bay platform RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28EB719AZIT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Tunnel Creek Queen’s Bay platform RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28EB733ALI | 制造商:Silicon Laboratories Inc 功能描述:4 OUTPUT PCI EXPRESS (PCIE) GEN1/2 WITH 25MHZ AND 33MHZ LVCM - Bulk 制造商:Silicon Laboratories Inc 功能描述:IC EMB CLOCK GENERATOR 32QFN |
| SL28EB733ALIT | 制造商:Silicon Laboratories Inc 功能描述:4 OUTPUT PCI EXPRESS (PCIE) GEN1/2 WITH 25MHZ AND 33MHZ LVCM - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC EMB CLOCK GENERATOR 32QFN |
| SL28EB740AZI | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Tunnel Creek Queen’s Bay platform RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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