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參數(shù)資料
| 型號： | SN54ABT8996FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS |
| 中文描述： | 10位可尋址掃描港口多點尋址IEEE標(biāo)準(zhǔn)1149.1的JTAG技術(shù)咨詢收發(fā)器 |
| 文件頁數(shù)： | 5/40頁 |
| 文件大?。?/td> | 564K |
| 代理商： | SN54ABT8996FK |
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SN54ABT8996, SN74ABT8996
10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS489C – AUGUST 1994 – REVISED APRIL 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
application information
In application, the ASP is used at each of several (serially-chained) groups of IEEE Std 1149.1-compliant
devices. The ASP for each such group is assigned an address (via inputs A9–A0) that is unique from that
assigned to ASPs for the remaining groups. Each ASP is wired at its primary TAP to common (multidrop) TAP
signals (sourced from a central IEEE Std 1149.1 bus master) and fans out its secondary TAP signals to the
specific group of IEEE Std 1149.1-compliant devices with which it is associated. An example is shown in
Figure 1.
ASP
IEEE Std 1149.1-
Compliant
Device Chain
P
P
P
P
P
S
S
S
S
S
A
A9–A0
ASP
IEEE Std 1149.1-
Compliant
Device Chain
P
P
P
P
P
S
S
S
S
S
A
A9–A0
ASP
IEEE Std 1149.1-
Compliant
Device Chain
P
P
P
P
P
S
S
S
S
S
A
A9–A0
TRST
TDO
TMS
TCK
TDI
IEEE
Std
1149.1
Bus
Master
To
Other
Modules
B
B
B
Figure 1. ASP Application
This application allows the ASP to be wired to a 4- or 5-wire multidrop test access bus, such as might be found
on a backplane. Each ASP would then be located on a module, for example a printed-circuit board (PCB), which
contains a serial chain of IEEE Std 1149.1-compliant devices and which would plug into the module-to-module
bus (e.g., backplane). In the complete system, the ASP shadow protocols would allow the selection of the scan
chain on a single module. The selected scan chain could then be controlled, via the multidrop TAP, as if it were
the only scan chain in the system. Normal IR and DR scans can then be performed to accomplish the module
test objectives.
Once scan operations to a given module are complete, another module can be selected in the same fashion,
at which time the ASP-based connection to the first module is dissolved. This procedure can be continued
progressively for each module to be tested. Finally, one of two global addresses can be issued to either leave
all modules unselected (disconnect address, DSA) or to deselect and reset scan chains for all modules (reset
address, RSA).
Additionally, in Pause-DR and Pause-IR TAP states, a third global address (test-synchronization address, TSA)
can be invoked to allow simultaneous TAP-state changes and multicast scan-in operations to selected modules.
This is especially useful in the former case, for allowing selected modules to be moved simultaneously to the
Run-Test-Idle TAP state for module-level or module-to-module built-in self-test (BIST) functions, which operate
synchronously to TCK in that TAP state, and in the latter case, for scanning common test setup/data into multiple
like modules.
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