- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373435 > SN54ABTH18504A (Texas Instruments, Inc.) Scan Test Devices With 20 Bit Universal Bus Transceivers(掃描檢測裝置，帶20位通用總線收發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | SN54ABTH18504A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Scan Test Devices With 20 Bit Universal Bus Transceivers(掃描檢測裝置，帶20位通用總線收發(fā)器) |
| 中文描述： | 掃描測試設備與20位通用總線收發(fā)器（掃描檢測裝置，帶20位通用總線收發(fā)器） |
| 文件頁數(shù)： | 15/35頁 |
| 文件大小： | 812K |
| 代理商： | SN54ABTH18504A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2
→
BIT 0
MSB
→
LSB
X00
DESCRIPTION
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudo-random pattern generation/40-bit mode (PRPG)
X10
Parallel-signature analysis/40-bit mode (PSA)
011
Simultaneous PSA and PRPG/20-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up/20-bit mode (PSA/COUNT)
While the control input BSCs (bits 47–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
the output-enable BSCs (bits 47–46 of the BSR) control the drive state (active or high impedance) of the selected
device output pins. These BCR instructions are valid only when the device is operating in one direction of data
flow (that is, OEAB
≠
OEBA). Otherwise, the bypass instruction is operated.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the
associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode
BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated
device I/O pins on each falling edge of TCK.
相關PDF資料 |
PDF描述 |
|---|---|
| SN54ABTH182646AHV | SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS |
| SN54ABTH18646AHV | SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS |
| SN54ABTH182646A | Scan Test Devices With 18 Bit Universal Bus Transceivers( 掃描檢測裝置，帶18位收發(fā)器和寄存器) |
| SN54ABTH1826520A | Scan Test Devices With 18 Bit Universal Bus Transceivers and Registers( 掃描檢測裝置，帶18位總線收發(fā)器和寄存器) |
| SN74ABTH1826520A | Scan Test Devices With 18 Bit Universal Bus Transceivers And Registers( 掃描檢測裝置帶18位總線收發(fā)器和寄存器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN54ABTH18504A_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS |
| SN54ABTH18504AHV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS |
| SN54ABTH18646A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS |
| SN54ABTH18646AHV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS |
| SN54ABTH18652A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS |
發(fā)布緊急采購，3分鐘左右您將得到回復。