參數(shù)資料
型號： SN54ABTH18504A
廠商： Texas Instruments, Inc.
英文描述： Scan Test Devices With 20 Bit Universal Bus Transceivers(掃描檢測裝置，帶20位通用總線收發(fā)器)
中文描述： 掃描測試設備與20位通用總線收發(fā)器（掃描檢測裝置，帶20位通用總線收發(fā)器）
文件頁數(shù)： 9/35頁
文件大?。?/td> 812K
代理商： SN54ABTH18504A
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JULY 1996
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
register overview
With the exception of the bypass and device-identification registers, any test register can be thought of as a
serial shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that
they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,
Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current
instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted
out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or
Update-DR), the shadow latches are updated from the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the four data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 3 lists the instructions supported by the ’ABTH18504A and ’ABTH182504A. The even-parity feature
specified for SCOPE
devices is supported in these devices. Bit 7 of the instruction opcode is the parity bit.
Any instructions that are defined for SCOPE
devices but are not supported by these devices default to
BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TDO
TDI
Bit 7
Parity
(MSB)
Bit 0
(LSB)
Figure 2. Instruction Register Order of Scan
相關PDF資料
PDF描述
SN54ABTH182646AHV SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SN54ABTH18646AHV SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SN54ABTH182646A Scan Test Devices With 18 Bit Universal Bus Transceivers( 掃描檢測裝置，帶18位收發(fā)器和寄存器)
SN54ABTH1826520A Scan Test Devices With 18 Bit Universal Bus Transceivers and Registers( 掃描檢測裝置，帶18位總線收發(fā)器和寄存器)
SN74ABTH1826520A Scan Test Devices With 18 Bit Universal Bus Transceivers And Registers( 掃描檢測裝置帶18位總線收發(fā)器和寄存器)
相關代理商/技術參數(shù)
參數(shù)描述
SN54ABTH18504A_08 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN54ABTH18504AHV 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN54ABTH18646A 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SN54ABTH18646AHV 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SN54ABTH18652A 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS
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