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參數(shù)資料
| 型號： | ST6228CN1 |
| 廠商： | 意法半導體 |
| 英文描述： | ER 3C 3#16S SKT RECP WALL |
| 中文描述： | 8位單片機與微控制器/ D轉換器，自動重加載定時器，UART的秘書長辦公室，安全復位和28引腳封裝 |
| 文件頁數(shù)： | 49/84頁 |
| 文件大?。?/td> | 561K |
| 代理商： | ST6228CN1 |
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49
ST62T28C/E28C
AUTO-RELOAD TIMER
(Cont’d)
AR Status Control Register 1(ARSC1)
Address: E7h
—
Read/Write
Bist 7-5 =
PS2-PS0
: Prescaler Division Selection
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits.Theprescaler division ratioislistedinthe
following table:
Table 16. Prescaler Division Ratio Selection
Bit 4 =
D4
: Reserved Must be kept reset.
Bit 3-2=
SL1-SL0
:Timer InputEdgeControl Bits 1-
0.These bits control theedge function of theTimer
input pinforexternalsynchronization.IfbitSL0isre-
set, edgedetectionis disabled; ifset edge detection
is enabled.If bit SL1 is reset,theARTimer inputpin
is rising edgesensitive; if set, it is falling edge sen-
sitive.
Bit 1-0 =
CC1-CC0
: Clock Source Select Bit 1-0.
These bits select theclock source for theAR Timer
through the AR Multiplexer. The programming of
the clocksources isexplainedin thefollowingTable
17:
Table 17. ClockSource Selection.
AR Load Register ARLR
. The ARLR loadregister
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
AR Load Register (ARLR)
Address: EBh
—
Read/Write
Bit 7-0 =
D7-D0
: Load Register Data Bits. These
are the load register data bits.
AR Reload/Capture Register
. The ARRC reload/
capture register is used to hold the auto-reload
value which is automatically loaded into the coun-
ter when overflow occurs.
AR Reload/Capture (ARRC)
Address: E9h
—
Read/Write
Bit 7-0 =
D7-D0
: Reload/Capture Data Bits These
are the Reload/Capture register data bits.
AR Compare Register
. The CP compare register
is used to holdthe compare value for the compare
function.
AR Compare Register (ARCP)
Address: EAh
—
Read/Write
Bit 7-0 =
D7-D0
: Compare Data Bits These are
the Compare register data bits.
7
0
PS2
PS1
PS0
D4
SL1
SL0
CC1
CC0
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
ARPSC Division Ratio
1
2
4
8
16
32
64
128
SL1
X
0
1
SL0
0
1
1
Edge Detection
Disabled
Rising Edge
Falling Edge
CC1
0
0
1
1
CC0
0
1
0
1
Clock Source
F
int
F
int
Divided by 3
ARTIMin Input Clock
Reserved
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST6228CN1/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| ST6228CN3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE |
| ST6228CN3/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| ST6228CN6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE |
| ST6228CN6/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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