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參數(shù)資料
| 型號： | ST6228CN1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | ER 3C 3#16S SKT RECP WALL |
| 中文描述： | 8位單片機(jī)與微控制器/ D轉(zhuǎn)換器，自動(dòng)重加載定時(shí)器，UART的秘書長辦公室，安全復(fù)位和28引腳封裝 |
| 文件頁數(shù)： | 52/84頁 |
| 文件大?。?/td> | 561K |
| 代理商： | ST6228CN1 |
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ST62T28C/E28C
4.5 U. A. R. T. (Universal Asynchronous Receiver/Transmitter)
The UART provides the basic hardware for asyn-
chronous serial communication which, combined
with anappropriate software routine, gives a serial
interface providing communication with common
baud rates (up to 76,800 Baud with an 8MHz ex-
ternal oscillator) and flexible character formats.
Operating in Half-Duplex mode only, the UART
uses a 10-bit frame or a 11-bit frame according to
the choosen MCU option. Automatic paritybit gen-
eration is software selectable in the 10-bit charac-
ter format allowing either 7 data bit + 1 parity bit, or
8 databittransmission. Transmitted datais sent di-
rectly, while received data is buffered allowing fur-
ther data characters to be received while the data
is beingreadout ofthe receive bufferregister. Data
transmit has priority over data being received.
The UART is supplied with an MCU internal clock
that isalsoavailableinWAITmodeoftheprocessor.
4.5.1 Ports Interfacing
RXD reception line and TXD emission line are
sharing the same external pins as two I/O lines.
Therefore, UART configuration requires to set
these two I/O lines through the relevant ports reg-
isters. The I/O line common with RXD line must be
defined as input mode (with or without pull-up)
while the I/O line common with TXD line must be
defined as output mode (Push-pull or open drain).
In the 11-bit character format option, the transmit-
ted data is inverted and can therefore use a single
transistor buffering stage. Defined as input, the
RXD line can be read at any time as an I/O line
during theUART operation. The TXD pin follows I/
O port registers value when UARTOE bit is
cleared, which means when no serial transmission
is in progress. As a consequence, a permanent
high level has to be written onto the I/O port in or-
der to achieve a proper stop condition on the TXD
line when no transmission is active.
Figure 30. UART Block Diagram
C
T
START
DETECTOR
DATA SHIFT
REGISTER
D8 D7 D6 D5 D4 D3 D2 D1 D0
CONTROL REGISTER
BAUD RATE
RECEIVE BUFFER
REGISTER
PROGRAMMABLE
DIVIDER
DIN
DOUT
D8
BAUD RATE x 8
WRITE
READ
RXD1
TXD1
UARTOE
RX and TX
INTERRUPTS
TXD
DR
0
MUX
1
f
OSC
VR02009
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST6228CN1/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| ST6228CN3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE |
| ST6228CN3/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| ST6228CN6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE |
| ST6228CN6/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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