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參數(shù)資料
| 型號(hào)： | ST62E40B |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁(yè)數(shù)： | 13/72頁(yè) |
| 文件大?。?/td> | 445K |
| 代理商： | ST62E40B |
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ST62T40B/E40B
MEMORY MAP
(Cont’d)
1.3.7 EEPROM Description
EEPROM memory is located in 64-byte pages in
data space. This memory may be used by theuser
program for non-volatile data storage.
Data space from 00h to3Fh is paged as described
in Table 7. EEPROM locations are accessed di-
rectly by addressing these paged sections of data
space.
The EEPROM does not require dedicated instruc-
tions forreadorwrite access. Onceselectedviathe
Data RAM Bank Register, the active EEPROM
page is controlled by the EEPROM Control Regis-
ter (EECTL), which is described below.
Bit E20FFofthe EECTL registermust beresetprior
to any write or read access to the EEPROM. If no
bank hasbeen selected, orif E2OFFis set,any ac-
cess is meaningless.
Programming must be enabled by setting the
E2ENA bit of the EECTL register.
The E2BUSY bit of the EECTL register is setwhen
the EEPROM is performing a programming cycle.
Any access to the EEPROM when E2BUSY is set
is meaningless.
Provided E2OFF and E2BUSY are reset, an EEP-
ROM location is read just like any other data loca-
tion, also in terms of access time.
Writing to the EEPROM may be carried out in two
modes: Byte Mode (BMODE) and Parallel Mode
(PMODE). In BMODE, one byte is accessed at a
time, while in PMODE up to 8 bytes in the same
row are programmed simultaneously (with conse-
quent speed and power consumption advantages,
the latter being particularly important in battery
powered circuits).
General Notes
:
Data should be written directly to the intended ad-
dress in EEPROM space.There is nobuffer mem-
ory between data RAM and the EEPROM space.
When the EEPROM is busy (E2BUSY = “1”)
EECTL cannot be accessed in write mode, it is
only possible to read the status of E2BUSY. This
implies that as long as the EEPROM is busy, it is
not possible to change the status of the EEPROM
Control Register. EECTL bits 4 and 5 are reserved
and must never be set.
Care is required when dealing withthe EECTL reg-
ister, as some bits are write only. For this reason,
the EECTL contents must not be altered while ex-
ecuting an interrupt service routine.
If it is impossible to avoid writing to this register
within an interrupt service routine, an image of the
register must be saved in a RAM location, and
each time the program writes to EECTL it must
also write to the image register. The imageregister
must be written to first so that, if an interrupt oc-
curs between the two instructions, the EECTL will
not be affected.
Table 7. Row Arrangement for Parallel Writing of EEPROM Locations
Dataspace
addresses.
Banks 0and 1.
Byte
ROW7
ROW6
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
0
1
2
3
4
5
6
7
38h-3Fh
30h-37h
28h-2Fh
20h-27h
18h-1Fh
10h-17h
08h-0Fh
00h-07h
Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.
The number of available 64-byte banks (1 or 2) is device dependent.
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