參數(shù)資料
型號: ST62E40B
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù): 37/72頁
文件大?。?/td> 445K
代理商: ST62E40B
37/72
37
ST62T40B/E40B
I/O PORTS
(Cont’d)
4.1.3 LCD alternate functions (combiports)
PC0 to PC7 can also be individually defined as 8
LCD segment output by setting DDRC, ORC and
DRC registers as shown in Table 15.
On the contrary with other I/O lines, the reset state
is theLCD output mode. These8 segment lines are
recognised as S33..S40 by the embedded LCD
controller drive.
4.1.4 SPI alternate functions
PB6/Sin and PB5/Scl pins must be configured as
input through the DDR and OR registers to be
used data in and data clock (Slave mode) for the
SPI. Allinput modesare available and I/O’s can be
read independantly of the SPI at any time.
PB7/Sout must be configured inopen drain output
mode to be used as data out for the SPI. In output
mode, thevalue present on the pin is the port data
register content only if PB7 is defined as push pull
output, while serial transmission is possible only in
open drain mode.
Table 15. PC0-PC7 Combiport Option Selection
Note:
X = Don’t care
Figure 20. Peripheral Interface Configuration of SPI
DDR
0
0
0
0
1
1
OR
0
0
1
1
0
1
DR
0
1
0
1
X
X
Mode
Input
Input
Input
Input
Output
Output
Option
With pull-up, no interrupt
No pull-up, no interrupt
With pull-up and with interrupt
LCD segment (Reset state)
Open-drain output
Push-pull output
PB7/Sout
PB6/Sin
PB5/Scl
PID
OPR
DR
1
MUX0
OUT
IN
SYNCHRONOUS
SERIAL I/O
CLOCK
PID
DR
PID
DR
PP/OD
VR01661F
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