參數(shù)資料
型號: ST62E40B
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù): 29/72頁
文件大?。?/td> 445K
代理商: ST62E40B
29/72
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ST62T40B/E40B
INTERRUPTS
(Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable theindividual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused.
Bit 6 =
LES
: Level/Edge Selection bit
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 =
ESB
: Edge Selection bit
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4=
GEN
: Global Enable Interrupt When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive butcannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt
ST62E40B/T40B are summarized in the Table 12
with associated mask bit to enable/disable the in-
terrupt request.
sources
available
on
the
Table 12. Interrupt Requests and Mask Bits
7
0
-
LES
ESB
GEN
-
-
-
-
Peripheral
Register
Address
Register
C8h
D4h
D7h
D1h
C2h
C0h-C4h
C1h-C5h
C6h-CFh
DAh
DBh
Mask bit
Masked Interrupt Source
Interrupt
source
All
GENERAL
TIMER 1
TIMER 2
A/D CONVERTER
SPI
Port PAn
Port PBn
Port PCn
PSS
32kHz OSC
IOR
TSCR1
TSCR2
ADCR
SPI
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
PSSCR
32OCR
GEN
All Interrupts, excluding NM
I
ETI
TMZ: TIMER Overflow
source 3
EAI
ALL
ORPAn-DRPAn
ORPBn-DRPBn
ORPCn-DRPCn
PEI
EOSCI
EOC: End of Conversion
End of Transmission
PAn pin
PBn pin
PCn pin
PIF:
OSCEOC
source 4
source 1
source 2
source 2
source 2
source 0
source 3
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