參數(shù)資料
型號(hào)： STPCCONSUMER-S
廠商： 意法半導(dǎo)體
英文描述： CONNECTOR ACCESSORY
中文描述： 連接器附件
文件頁(yè)數(shù)： 26/51頁(yè)
文件大?。?/td> 836K
代理商： STPCCONSUMER-S
STRAP OPTIONS
26/51
Release 1.4
Release B
This is preliminary information on a new product now in developement. Details are subject tochange without notice
Note;
1) This Strap Option selects between two different functional blocks, the first is the ISA and the other is
the VGA block.
3.1 STRAP REGISTER DESCRIPTION
Strap Option [16:0] are reserved.
3.1.1 STRAP REGISTER 2 INDEX 4CH (STRAP2)
Bits 4-0 of this register reflect the status of pins MD[20:16] respectively. Bit 5 of this register reflectthe sta-
tus of pin MD[23]. Bit 4 is writeable, writesto other bits in this registerhave no effect. Theyare use by the
chip as follows:
Bit 4-2; Reserved
Bit 1; This bit reflects the
value sampled on MD[17] pin
and controls the PCI clock output as follows:
0: PCI clock output = HCLK / 2
1: PCI clock output = HCLK / 3
Bit 0; Reserved
This register defaults to the values sampled on MD[23] & MD[20:16] pins after reset.
3.1.2 HCLK PLL STRAP REGISTER 0 INDEX 5FH (HCLK_Strap)
Bits 5-0 of this register reflect the status of pins MD[26:21] respectively.
They are use by the chip as follows:
Bits 5-3 These pins reflectthe
value sampled on MD[26:24] pins
respectively and control the Host clock
frequency synthesizer.
Bit 2-0; Reserved
This register defaults to the values sampled on above pins after reset.
MD39
MD40
MD41
MD42
MD43
Reserved
CPU Mode
Reserved
Reserved
Reserved
Pull up
User defined
Pull down
Pull down
Pull down
CPU
DX1
DX2
Memory
Data
Lines
Note
Refer to
Designation
Location
Actual
Settings
Set to ’0’
Set to ’1’
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