參數(shù)資料
型號： STPCCONSUMER-S
廠商： 意法半導(dǎo)體
英文描述： CONNECTOR ACCESSORY
中文描述： 連接器附件
文件頁數(shù)： 12/51頁
文件大?。?/td> 836K
代理商： STPCCONSUMER-S
PIN DESCRIPTION
12/51
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
IOR#, IOW#
MCS16#, IOCS16#
BHE#
ZWS#
REF#
MASTER#
AEN
IOCHCK#
IOCHRDY
ISAOE#
GPIOCS#
IRQ_MUX[3:0]
DREQ_MUX[1:0]
DACK_ENC[2:0]
TC
RTCAS
RMRTCCS#
KBCS#
RTCRW#
RTCDS
I/O
I
O
I
O
I
O
I
I/O
O
I/O
I
I
O
O
O
I/O
I/O
I/O
I/O
I/O Read and Write
Memory/IO Chip Select16
System Bus High Enable
Zero Wait State
Refresh Cycle.
Add On Card Owns Bus
Address Enable
I/O Channel Check.
I/O Channel Ready (ISA) - Busy/Ready (IDE)
ISA/IDE Selection
General Purpose Chip Select
Time-Multiplexed Interrupt Request
Time-Multiplexed DMA Request
Encoded DMA Acknowledge
ISA Terminal Count
Real Time Clock Address Strobe
ROM/RTC Chip Select
Keyboard Chip Select
RTC Read/Write
RTC Data Strobe
2
2
1
1
1
1
1
1
1
1
1
4
2
3
1
1
1
1
1
1
LOCAL BUS
PA[21:0]
PD[15:0]
PRD1#,PRD0#
PWR1#,PWR0#
PRDY#
FCS1#, FCS0#
IOCS#[3:0]
O
I/O
O
O
I
O
O
Address Bus
Data Bus
Peripheral Read Control
Peripheral Write Control
Data Ready
Flash Chip Select
I/O Chip Select
22
16
2
2
1
2
4
IDE CONTROL
DA[2:0]
DD[15:0]
PCS3#,PCS1#,SCS3#,SCS1#
DIORDY
PIRQ, SIRQ
PDRQ, SDRQ
PDACK#, SDACK#
PDIOR#, SDIOR#
PDIOW#, SDIOW#
O
I/O
O
O
I
I
O
O
O
Address Bus
Data Bus
Primary & Secondary Chip Selects
Data I/O Ready
Primary & Secondary Interrupt Request
Primary & Secondary DMA Request
Primary & Secondary DMA Acknowledge
Primary & Secondary I/O Channel Read
Primary & Secondary I/O Channel Write
3
16
4
1
2
2
2
2
2
MONITOR INTERFACE
RED, GREEN, BLUE
VSYNC
HSYNC
VREF_DAC
RSET
COMP
O
O
O
I
I
I
Analog Red, Green, Blue
Vertical Sync
Horizontal Sync
DAC Voltage reference
Resistor Set
Compensation
3
1
1
1
1
1
Table 2.2. Definition of Signal Pins
Signal Name
Dir
Description
Qty
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