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參數(shù)資料
| 型號： | T431616D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| 中文描述： | 100萬× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數(shù)： | 1/74頁 |
| 文件大?。?/td> | 781K |
| 代理商： | T431616D |
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TE
CH
tm
T431616D/E
TM Technology Inc. reserves the right
P. 1
Publication Date: FEB. 2007
to change products or specifications without notice.
Revision: A
SDRAM
1M x 16 SDRAM
512K x 16bit x 2Banks Synchronous DRAM
FEATURES
Fast access time: 5/6/7 ns
Fast clock rate: 200/166/143 MHz
Self refresh mode: standard and low power
Internal pipelined architecture
512K word x 16-bit x 2-bank
Programmable Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Individual byte controlled by LDQM and UDQM
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
JEDEC standard +3.3V±0.3V power supply
Interface: LVTTL
50-pin 400 mil plastic TSOP II package
60-ball, 6.4x10.1mm VFBGA package
Lead Free Package available for both TSOP II and
VFBGA
Low Operating Current for T431616E
Key Specifications
T431616D/E
-5/6/7
tCK3 Clock Cycle time(min.)
5/6/7ns
tRAS Row Active time(max.)
35/42/42 ns
tAC3 Access time from CLK(max.)
4.5/5/5.5 ns
tRC
Row Cycle time(min.)
48/54/63 ns
ORDERING INFORMATION
Part Number
Frequency
Package
T431616D-5S/C
200MHz
TSOP II / VFBGA
T431616D-5SG/CG
200MHz
TSOP II / VFBGA
T431616D-6S/C
166MHz
TSOP II / VFBGA
T431616D-6SG/CG
166MHz
TSOP II / VFBGA
T431616D-7S/C
143MHz
TSOP II / VFBGA
T431616D-7SG/CG
143MHz
TSOP II / VFBGA
T431616E-7S/C
143MHz
TSOP II / VFBGA
T431616E-7SG/CG
143MHz
TSOP II / VFBGA
G : indicates Lead Free Package
GRNERAL DESCRIPTION
The T431616D/E SDRAM is a high-speed CMOS
synchronous DRAM containing 16 Mbits. It is internally
configured as a dual 512K word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
512K x 16 bit banks is organized as 2048 rows by 256
columns by 16 bits. Read and write accesses to the
SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which
is then followed by a Read or Write command.
The T431616D/E provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy to
use. By having a programmable mode register, the
system can choose the most suitable modes to maximize
its performance. These devices are well suited for
applications requiring high memory bandwidth and
particularly well suited to high performance PC
applications
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T431616D-5C | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-5CG | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-5S | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-5SG | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-6C | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
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