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參數(shù)資料
| 型號： | T431616D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| 中文描述： | 100萬× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數(shù)： | 67/74頁 |
| 文件大?。?/td> | 781K |
| 代理商： | T431616D |
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TE
CH
tm
T431616D/E
TM Technology Inc. reserves the right
P. 7
Publication Date: FEB. 2007
to change products or specifications without notice.
Revision: A
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks earlier (i.e.
LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto precharge function may
be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end
of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The
interrupt coming from the Read command can occur on any clock cycle following a previous Read command
(refer to the following figure).
CLK
COMM AND
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
T0
T1
T2T3
T4T5
T6T7
T8
READ A
READ B
NOP
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from
a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior to the Write command
to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-
impedance on the DQ pins must occur between the last read data and the Write command (refer to the following
three figures). If the data output of the burst read occurs at the second clock of the burst write, the
LDQM/UDQM must be asserted (HIGH) at least one clock prior to the Write command to avoid internal bus
contention.
READ A
NOP
WRITE B
NOP
CLK
DQM
COM MAND
DQ's
T0
T1
T2T3
T4T5
T6
T7
T8
NOP
DOUT A0
DINB0
DINB1
DI NB2
Must be Hi-Z before
the Write Command
: "H" or "L"
Read to Write Interval (Burst Length
≥≥≥≥ 4, CAS# Latency = 3)
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| T431616D-5C | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
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| T431616D-5S | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
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