參數(shù)資料
型號: T48C862x-Rf-TNS
廠商: Atmel Corp.
元件分類: 4位微控制器
英文描述: Microcontroller with UHF ASK/FSK Transmitter
中文描述: 微控制器,帶有超高頻ASK / FSK發(fā)射器
文件頁數(shù): 60/108頁
文件大小: 1023K
代理商: T48C862X-RF-TNS
60
T48C862-R4 [Preliminary]
4551C–4BMCU–01/04
Timer 3 – Mode 10:
Manchester
Demodulation/Pulse-width
Demodulation
For Manchester demodulation, the edge detection stage must be programmed to detect
each edge at the input. These edges are evaluated by the demodulator stage. The timer
stage is used to generate the shift clock for the SSI. The compare register 1 match
event defines the correct moment for shifting the state from the input T3I as the decoded
bit into shift register - after that the demodulator waits for the next edge to synchronize
the timer by a reset for the next bit. The compare register 2 can also be used to detect a
time-out error and handle it with an interrupt routine (see “Combination Mode 8:
Manchester Demodulation/Pulse-width Demodulation” on page 83).
Figure 59.
Manchester Demodulation
Timer 3 – Mode 11:
Biphase Demodulation
In the Biphase demodulation mode, the timer operates like in Manchester demodulation
mode. The difference is that the bits are decoded via a toggle flip-flop. This flip-flop sam-
ples the edge in the middle of the bitframe and the compare register 1 match event
shifts the toggle flip-flop output into shift register (see “Combination Mode 9: Biphase
Demodulation” on page 84).
Figure 60.
Biphase Demodulation
1
0
1
1
1
0
0
1
1
0
1
1
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
Synchronize
Manchester demodulation mode
Timer 3
mode
T3EX
SI
SR-DATA
T3I
CM31=SCI
1
0
0
1
1
0
0
1
1
1
1
0
1
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
Synchronize
Biphase demodulation mode
Timer 3
mode
T3EX
Q1=SI
CM31=SCI
SR-DATA
0
0
0
0
T3I
Reset
Counter 3
1
0
1
0
1
0
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