參數(shù)資料
型號(hào)： T48C862x-Rf-TNS
廠商： Atmel Corp.
元件分類： 4位微控制器
英文描述： Microcontroller with UHF ASK/FSK Transmitter
中文描述： 微控制器，帶有超高頻ASK / FSK發(fā)射器
文件頁(yè)數(shù)： 68/108頁(yè)
文件大?。?/td> 1023K
代理商： T48C862X-RF-TNS
68
T48C862-R4 [Preliminary]
4551C–4BMCU–01/04
Figure 64.
Block Diagram of the Synchronous Serial Interface
General SSI Operation
The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buff-
ers –
the receive buffer (SRB) for capturing the incoming serial data and a transmit
buffer (STB) for intermediate storage of data to be serially output. Both buffers are
directly accessable by software. Transferring the parallel buffer data into and out of the
shift register is controlled automatically by the SSI control, so that both single byte trans-
fers or continuous bit streams can be supported.
The SSI can generate the shift clock (SC) either from one of several on-chip clock
sources or accept an external clock. The external shift clock is output on, or applied to
the Port BP40. Selection of an external clock source is performed by the Serial Clock
Direction control bit (SCD). In the combinational modes, the required clock is selected
by the corresponding timer mode.
The SSI can operate in three data transfer modes –
synchronous 8-bit shift mode, a
9-bit Multi-Chip Link Mode (MCL) ,or 8-bit pseudo MCL protocol (without acknowledge-
bit).
External SSI clocking is not supported in these modes. The SSI should thus generate
and has full control over the shift clock so that it can always be regarded as an MCL bus
master device.
All directional control of the external data port used by the SSI is handled automatically
and is dependent on the transmission direction set by the Serial Data Direction (SDD)
control bit. This control bit defines whether the SSI is currently operating in Transmit
(TX) mode or Receive (RX) mode.
Serial data is organized in 8-bit telegrams which are shifted with the most significant bit
first. In the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the
telegram for handshaking purposes (see “MCL Bus Protocol” on page 72).
At the beginning of every telegram, the SSI control loads the transmit buffer into the shift
register and proceeds immediately to shift data serially out. At the same time, incoming
data is shifted into the shift register input. This incoming data is automatically loaded
into the receive buffer when the complete telegram has been received. Thus, data can
be simultaneously received and transmitted if required.
8-bit Shift Register
MSB
LSB
Shift_CL
SO
SIC1
SIC2
SISC
SC
Control
STB
SRB
SI
Timer 2 / Timer 3
Output
INT3
SC
I/O-bus
I/O-bus
SSI-Control
TOG2
POUT
T1OUT
SYSCL
SO
SI
MCL_SC
SD
MCL_SD
Transmit
Buffer
Receive
Buffer
SCI
/2
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