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參數(shù)資料
| 型號： | T7121 |
| 英文描述： | T7121 HDLC Interface for ISDN |
| 中文描述： | T7121的HDLC接口用于ISDN |
| 文件頁數(shù)： | 12/68頁 |
| 文件大小： | 685K |
| 代理商： | T7121 |
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12
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
5-5029
Figure 3. Transmitting with a Gated Clock
The receiver can be enabled or disabled by programming the ENR bit (R6—B2). When disabled, the receiver
ignores all serial inputs (i.e., no data loaded into the FIFO). Whatever was in the FIFO before the receiver was dis-
abled remains intact, and the microprocessor can read the contents as normal. Disabling the receiver does
cause a receiver reset. Whenever the receiver has been enabled and is subsequently disabled, the receiver must
be reset via RRES (R6—B4) before it is reenabled.
not
The HIFI-64 can receive data on either of two receive data pins (DRA, pin 20, or DRB, pin 21) depending on the
programming of the DRA/B bit in register 8 (R8—B7). The HIFI-64 can be programmed to use either the input of pin
21 (CLKR/DRB) or the input of pin 18 (CLKX) as the receive clock using P21CTL (R5—B6). Clearing P21CTL to 0
(DEFAULT) selects pin 21, while a setting of 1 selects pin 18. The selected clock can be programmed to latch
received data on either clock edge using CLKRI (R9—B0). Setting CLKRI to 1 causes the receiver to use the posi-
tive receive clock edge to latch data, while clearing CLKRI to 0 causes the receiver to use the negative edge.
Whenever the clock edge is changed, the receiver should be reset via an RRES (R6—B4). When a gated clock is
used, the receiver begins latching data on the first programmed clock edge. When a gated clock is used, separate
transmit and receive clocks must be used if data alignment to the first clock edge is required, since the transmit
clock requires an extra edge to align. See Figures 3 and 4.
5-5030
Figure 4. Receiving with a Burst Clock
CLKX
DXA
TRANSMIT 1ST BIT ON 1ST POSITIVE EDGE AFTER 1ST NEGATIVE EDGE
FIRST BYTE TRANSMITTED
SECOND BYTE TRANSMITTED
SET
CLOCK
EDGES
VIA R9
RESET
TRANSMITTER
VIA R6—B5
BIT VALUE
MAINTAINED
UNTIL NEXT EDGE
CLKR
DRA
LATCH IN 1ST RECEIVE BIT ON 1ST NETGATIVE EDGE AFTER RECEIVE RESET
FIRST DATA BYTE
SECOND DATA BYTE
SET
CLOCK
EDGES
VIA R9
RESET
RECEIVER
VIA R6—B4
B0
B7
B0
B7
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|---|---|
| T7121-EL2 | T7121 HDLC Interface for ISDN |
| T7121-PL2 | T7121 HDLC Interface for ISDN |
| T7121 | HDLC Interface for ISDN (HIFI-64)(應用于ISDN的HDLC（高階數(shù)據(jù)鏈路）接口) |
| T7502 | T7502 Dual PCM Codec with Filters |
| T7503 | T7503 Dual PCM Codec with Filters |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T7-121A1 | 制造商:OTTO 功能描述:Toggle Switches ON NONE OFF 1 Pole Standard Bat Handle 制造商:OTTO Engineering Inc 功能描述:Switch Toggle ON None OFF SPST Bat Toggle Screw 16A 115VAC 28VDC Panel Mount with Threads |
| T7-121A2D | 制造商:OTTO 功能描述:Toggle Switches ON NONE OFF 1 Pole Standard LeverLock 制造商:OTTO Engineering Inc 功能描述:1 POLE, SCREW, STD, |
| T7-121A2G | 功能描述:撥動開關 ON NONE OFF 1 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明: |
| T7-121A5 | 制造商:OTTO 功能描述:Toggle Switches ON NONE OFF 1 Pole Standard Bat Handle 制造商:OTTO Engineering Inc 功能描述:Switch Toggle ON None OFF SPST Bat Toggle Screw 16A 115VAC 28VDC Panel Mount with Threads |
| T7-121B1 | 功能描述:撥動開關 ON NONE ON 1 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明: |
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