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參數(shù)資料
| 型號： | T7121 |
| 英文描述： | T7121 HDLC Interface for ISDN |
| 中文描述： | T7121的HDLC接口用于ISDN |
| 文件頁數(shù)： | 13/68頁 |
| 文件大小： | 685K |
| 代理商： | T7121 |
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Lucent Technologies Inc.
13
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
Time-Slot Feature
The HIFI-64 can be configured to interface with devices
supplying a frame-synchronization signal (FS) to indi-
cate the beginning of a single or multiple time-slot
sequence. The T7121 can be configured to interface to
TDM highways from 3 to 64 time slots.
The HWYEN bit (R0—B7) enables the time-slot feature
logic. All highway parameters should be programmed
before enabling HWYEN. When HWYEN is 0, any input
on the FS pin is ignored. When HWYEN is 1, data
transmission begins with the first programmed time slot
following the first detected frame sync, provided that at
least one of the transmit pins is enabled and at least
one transmit bit is unmasked. The first data byte trans-
mitted in all cases is FF hex. When transmit highway
parameters are changed, such as time slot, the trans-
mitter and transmit output pins should be disabled
(ENT R6—B3 = 0, DXBC R7—B6 = 0, DXAC R7—B7 =
0). This guarantees that no other time slot is corrupted
during reprogramming. When the receiver time slot is
changed, the receiver should be disabled (ENR
R6—B2 = 0). After reprogramming, 1 TDM frame is
necessary to resynchronize. When HWYEN is first
enabled, the user should wait one TDM frame between
enabling HWYEN and enabling the transmit outputs.
The highway logic is reset completely to a known state
by each FS pulse or by a full chip reset.
The T7121 provides a bit masking feature to allow sub-
rate operation. The default bit masks are FF hexadeci-
mal for the receiver bit mask (R12) and 00 hexadecimal
for the transmitter bit mask (R13). The transmitter by
default transmits no bits in the selected time slot. To
enable transmission of all 8 bits in the selected time
slot, the transmitter bit mask (R13) must be changed to
FF hexadecimal (see the Bit Masking section for more
details).
The HIFI-64 determines that an FS has occurred by
sampling the FS signal with the appropriate data clock.
The polarity of a valid FS is determined by FSPOL
(R0—B6). That is, if FSPOL is 0, the FS is considered
valid when low. When FSPOL is 1, the FS is consid-
ered valid when high. When an FS pulse is provided, at
least one FS pulse must be provided for every 512 data
clock cycles. The FE bit (R0—B5) controls the edge of
the data clock used to sample the FS signal. If FE
(R0—B5) is cleared to 0, FS is sampled on a negative
edge of the transmit and receive data clocks. If FE is
set to 1, FS is sampled on a rising edge of the transmit
and receive data clocks.
The HIFI-64 can be programmed to transmit data on
either a positive or negative edge of the data clock by
programming the CLKXI bit (R9—B4). Similarly, the
device can be programmed to sample received data on
either a positive or negative edge of the data clock by
programming the CLKRI bit (R9—B0). The timing of the
transmission or reception of the first bit relative to the
frame-sync pulse then depends on the configuration of
three bits: FE (R0—B5), CLKXI (R9—B4), and CLKRI
(R9—B0). Figure 12 in the Timing Characteristics sec-
tion shows the position of the first transmit bit and
receive bit relative to the FS for each combination of
these register bits. These register configurations are
assumed:
HWYEN (R0—B7)
FSPOL (R0—B6)
TBOF[2—0] (R9—B[7—5])
RBOF[2—0] (R9—B[3—1])
TSLT[5—0] (R7—B[5—0])
RSLT[5—0] (R8—B[5—0])
=
=
=
=
=
=
1
1
000
000
000000
000000
Figure 13 in the Timing Characteristics section shows
an example of bit masking; all other examples assume
no masking. Transmission can be over DXA and/or
DXB (depending on the configuration of the DXAC and
DXBC bits in register 7 [R7—B6,7]), and
TSCA
is
shown to illustrate transmission over DXA with an
external driver. DRA or DRB can be used to receive
incoming data (depending on configuration of the DRA/
B bit [R8—B7]).
The HIFI-64 can be programmed to delay transmission
of the first bit by using the offset registers. These are
the transmit bit offset TBOF (R9—B[7—5]), the transmit
time-slot TSLT (R7—B[5—0]), and the transmitter time-
slot offset TTSOF (R10—B[5—0]). The transmit bit off-
set register moves the transmission of the first bit for-
ward one bit at a time, up to 7 bits total. The transmitter
time-slot offset moves the first bit forward by multiples
of 8 bits. The combination of the settings of these two
registers defines the position of time slot 0. From that
point, the time slot is selected by the value of the trans-
mitter time slot TSLT (R7—B[5—0]). The first bit is
transmitted
TBOF + (8 x TTSOF) + (8 x TSLT) = N
bit times after the beginning of the TDM frame.
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