參數(shù)資料
型號(hào)： T7121
英文描述： T7121 HDLC Interface for ISDN
中文描述： T7121的HDLC接口用于ISDN
文件頁(yè)數(shù)： 6/68頁(yè)
文件大?。?/td> 685K
代理商： T7121
6
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
17
DXB/
TSCA
O
Transmit Data B or Time-Slot Control for DXA.
user-controlled by the P17CTL bit in the receiver control register (R5—B7).
Clearing the P17CTL bit to 0 selects operation as Transmit Data B. Once DXB
operation is selected, data is transmitted on DXB whenever the DXBC bit in reg-
ister 7 (R7—B6) is set to 1. Data can be configured for transmission on either
CLKX edge (CLKXI, R9—B4), optionally inverted (DXI, R10—B7) and placed in
a user-selected time slot (registers 7, 9, 10) with bit 0 or bit 7 sent first (TLBIT,
R10—B6).
The functionality of this pin is
DXB should be pulled up by an external resistor to prevent random data pat-
terns from propagating through other devices when DXB is 3-stated.
When P17CTL (R5—B7) is set to 1, this pin is configured as
(time-slot control for DXA).
TSCA
when data is being transmitted on DXA over long distances.
ing the valid bit positions of data and is high at all other times.
TSCA
(active-low)
allows use of an external 3-stating bus driver
TSCA
goes low dur-
When an external driver is required, DXAC (R7—B7) must be set to 1. Setting
the P17CTL bit (R5—B7) to 1 overrides the selection of DXBC (R7—B6).
Transmit Clock.
This input clock controls the bit rate for transmitted data. Trans-
mit clock frequency must be less than the chip master clock frequency divided
by 2 (fCLKX < fCLK/2). In the reset configuration, data is transmitted on the fall-
ing edge of CLKX. Data can be transmitted by using the rising edge of CLKX by
setting the CLKX Invert bit (CLKXI) in the bit offset register (R9—B4) to 1. If the
P21CTL bit in the receiver control register (R5—B6) is set to 1, this clock is also
used to receive data. If P21CTL is 0, the transmit clock rate can be independent
of the receive clock rate.
Transmit Data A.
When the DXAC bit in register 7 (R7—B7) is set to 1, data is
transmitted on this pin. If external drivers are not required, both DXAC (R7—B7)
and DXBC (R7—B6) can be set to allow simultaneous transmission of the data
byte on both transmit data pins.
18
CLKX
I
19
DXA
O
Data can be configured for transmission on either CLKX edge (CLKXI, R9—B4),
optionally inverted (DXI, R10—B7) and placed in a user-selected time slot (reg-
isters 7, 9, 10) with bit 0 or bit 7 sent first (TLBIT, R10—B6).
DXA should be pulled up by an external resistor to prevent random data pat-
terns from propagating through other devices when DXA is 3-stated.
Receive Data A.
When the DRA/B bit in register 8 (R8—B7) is cleared to 0,
data is received on this pin. Data can be optionally inverted (DRI, R11—B7),
received on a positive or negative receive clock edge (CLKRI, R9—B0), and
received during a user-selected time slot (registers 8, 9, 11) with bit 0 or bit 7
first (RLBIT, R11—B6).
20
DRA
I
Table 2. Pin Descriptions
(continued)
Pin
Symbol
Type
Name/Function
Pin Information
(continued)
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