![](http://datasheet.mmic.net.cn/90000/MQ83C154DXXX-12-883R_datasheet_2377128/MQ83C154DXXX-12-883R_92.png)
92
2588F–AVR–06/2013
ATtiny261/461/861
counter value and so on. The definitions in
Table 12-1 are used extensively throughout the
document.
12.3
Clock Sources
The Timer/Counter is clocked internally, either from CK or PCK. See bits CSxx in
Table 12-17 on12.3.1
Prescaler
Figure 12-3 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchro-
nous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses
the system clock (CK) as a clock timebase and asynchronous mode uses the fast peripheral
clock (PCK) as a clock time base. The PCKE bit from the PLLCSR register enables the asyn-
chronous mode when it is set (‘1’).
Figure 12-3. Timer/Counter1 Prescaler
In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop,
and in the synchronous clocking mode the clock selections are from CK to CK/16384 and stop.
The frequency of the fast peripheral clock is 64 MHz or 32 MHz in Low Speed mode (the LSM bit
in PLLCSR register is set to one). The Low Speed Mode is recommended to use when the sup-
ply voltage below 2.7 volts are used.
Table 12-1.
Definitions
Constant
Description
BOTTOM
The counter reaches BOTTOM when it becomes 0x00
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255)
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the
value stored in the OCR0A Register. The assignment depends on the mode of operation
TIMER/COUNTER1 COUNT ENABLE
PSR1
CS10
CS11
CS12
PCK 64/32 MHz
0
CS13
14-BIT
T/C PRESCALER
T1CK/2
T1CK
T1CK/4
T1CK/8
T1CK/16
T1CK/32
T1CK/64
T1CK/128
T1CK/256
T1CK/512
T1CK/1024
T1CK/2048
T1CK/4096
T1CK/8192
T1CK/16384
S
A
CK
PCKE
T1CK