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2588F–AVR–06/2013
ATtiny261/461/861
12.12.10 OCR1B – Timer/Counter1 Output Compare Register B
The output compare register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does
only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and
OCR1B to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-
ing the compare event.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the
internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are
12.12.11 OCR1C – Timer/Counter1 Output Compare Register C
The output compare register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1, and a compare match will clear TCNT1. This register has the same function in
Normal mode and PWM modes.
Note that, if a smaller value than three is written to the Output Compare Register C, the value is
automatically replaced by three as it is a minumum value allowed to be written to this register.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the
internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are
12.12.12 OCR1D – Timer/Counter1 Output Compare Register D
The output compare register D is an 8-bit read/write register.
The Timer/Counter Output Compare Register D contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does
only occur if Timer/Counter1 counts to the OCR1D value. A software write that sets TCNT1 and
OCR1D to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1D after a synchronization delay follow-
ing the compare event.
Bit
76543210
MSB
LSB
OCR1B
Read/Write
R/W
Initial value
00000000
Bit
76543210
MSB
LSB
OCR1C
Read/Write
R/W
Initial value
11111111
Bit
76543210
MSB
LSB
OCR1D
Read/Write
R/W
Initial value
00000000