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| 型號(hào)： | T83C154DXXX-20 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁(yè)數(shù)： | 34/242頁(yè) |
| 文件大?。?/td> | 3080K |
| 代理商： | T83C154DXXX-20 |
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129
2588F–AVR–06/2013
ATtiny261/461/861
13.3.3
SPI Slave Operation Example
The following code demonstrates how to use the USI module as a SPI Slave:
init:
ldi
r16,(1<<USIWM0)|(1<<USICS1)
sts
USICR,r16
...
SlaveSPITransfer:
sts
USIDR,r16
ldi
r16,(1<<USIOIF)
sts
USISR,r16
SlaveSPITransfer_loop:
lds
r16, USISR
sbrs
r16, USIOIF
rjmp
SlaveSPITransfer_loop
lds
r16,USIDR
ret
The code is size optimized using only eight instructions (+ ret). The code example assumes that
the DO is configured as output and USCK pin is configured as input in the DDR Register. The
value stored in register r16 prior to the function is called is transferred to the master device, and
when the transfer is completed the data received from the Master is stored back into the r16
Register.
Note that the first two instructions are for initialization, only, and need only be executed once.
These instructions set three-wire mode and positive edge clock. The loop is repeated until the
USI Counter Overflow Flag is set.
13.3.4
Two-wire Mode
The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate lim-
iting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA.
Figure 13-4 on page 130 shows two USI units operating in two-wire mode, one as master and
one as slave. It is only the physical layer that is shown since the system operation is highly
dependent of the communication scheme used. The main differences between the master and
slave operation at this level is the serial clock generation which is always done by the master.
Only the slave uses the clock control unit.
Clock generation must be implemented in software, but the shift operation is done automatically
in both devices. Note that clocking only on negative edges for shifting data is of practical use in
this mode. The slave can insert wait states at start or end of transfer by forcing the SCL clock
low. This means that the master must always check if the SCL line was actually released after it
has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that the
transfer is completed. The clock is generated by the master by toggling the USCK pin via the
PORTA register.
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相關(guān)代理商/技術(shù)參數(shù) |
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| T83C154-L16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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| T83C154T-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| T83C154T-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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