參數(shù)資料
型號(hào)： T8531
元件分類(lèi)： Codec
英文描述： T8502 and T8503 Dual PCM Codecs with Filters
中文描述： T8502和T8503雙的PCM編解碼器與濾波器
文件頁(yè)數(shù)： 20/48頁(yè)
文件大?。?/td> 999K
代理商： T8531
20
Lucent Technologies Inc.
Preliminary Data Sheet
November 2000
Codec Chip Set
T8531/T8532 Multichannel Programmable
Chip Set Functional Description
(continued)
DSP Engine Timing
(continued)
Changing DSP RAM Space of an Active Time Slot
The microprocessor is only allowed to change four
RAM locations for an active time slot:
I
Relative transmit gain
I
Relative receive gain
I
Address of receive ac routine
I
Address of transmit ac routine
Absolute gains and time-slot assignment can only be
altered when the time slot is inactive. Note that the
DSP engine does not check the TCW of active time
slots.
Following the initial powerup, the line card is likely to be
in service without being reset for as long as it continues
to operate trouble-free. Therefore, the microprocessor
has the option of continuously monitoring the variables
it has programmed by reading them back from the DSP
engine/microprocessor interface and rewriting them.
DSP Engine Memory Requirements
The size of the DSP engine internal dual-port RAM is
4K x 16-bit words per DSP engine. RAM storage is
used for user-programmable variables and for interme-
diate storage of the data being processed by the
device. The RAM memory map is given in Table 18.
The on-chip ROM is used for both program and data.
The DSP engine firmware is ROM based. The hard-
ware development system code is also ROM based.
The DSP engine ROM memory map is given in
Table 41.
T8531 Reset and Start-Up
The chips support both hardware and software reset.
Hardware Reset
The T8531 reset functions are handled by the reset
control block. Hardware reset occurs if the board is
powered up with RSTB low. Since RSTB has a Schmitt
trigger buffer with an internal pull-up, a capacitor
attached external to the RSTB pin causes the pin to
pull high after a specified period of time. For power-on
reset, the T8531 requires that this period of time be
>1 ms to give the on-chip clock synthesizer block time
to start producing clock edges for the T8531 and
T8532 chips (although it may not have reached its final
accuracy yet). Successful hardware reset of the device
requires that:
1. The PCM bus signals SCK and SFS should be valid
at the start of the 1 ms power-on reset period.
2. V
DD
(and therefore RSTB) should have been low for
at least 200 ms prior to commencing power-on reset
to ensure that the JTAG controller powerup reset cir-
cuit has had time to clear the JTAG controller.
If, during normal operation, V
DD
falls below the defined
minimum value, V
DD
min, the power-on reset procedure
described above must be repeated.
Hardware reset occurs if RSTB is pulsed high-low-high
for 1 ms during normal operation (i.e., no loss of
power).
Table 7. Summary of Microprocessor Commands for Control of T8531 Data Processing
Function Required
Number of Commands
17
1
16 per channel
1
When Issued
Start-up
Bulk TSA register download & BCW2
Individual TSA register download
Coefficient download
Set TCW to use/share coefficients
already downloaded to default tables
Enable time slot via TCW (fixed TSA)
Enable time slot via TCW (dynamic TSA)
Disable time slot
Change gain value
Prior to activating a time slot via the TCW
Start-up or when time slot is inactive
Start-up or when time slot is inactive
1
2
1
When time slot is inactive
When time slot is inactive
When time slot is active
Any time
1 per gain
相關(guān)PDF資料
PDF描述
T8532 T8502 and T8503 Dual PCM Codecs with Filters
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T8531A 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:T8531A/8532 Multichannel Programmable Codec Chip Set
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T8533 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:T8533/34 Quad Programmable Line Card Signal Processor
T85331G 制造商:BITECH 制造商全稱(chēng):Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks
T85331J 制造商:BITECH 制造商全稱(chēng):Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks
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