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參數(shù)資料
| 型號： | T8531 |
| 元件分類： | Codec |
| 英文描述： | T8502 and T8503 Dual PCM Codecs with Filters |
| 中文描述： | T8502和T8503雙的PCM編解碼器與濾波器 |
| 文件頁數(shù)： | 8/48頁 |
| 文件大?。?/td> | 999K |
| 代理商： | T8531 |
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8
Lucent Technologies Inc.
Preliminary Data Sheet
November 2000
Codec Chip Set
T8531/T8532 Multichannel Programmable
Pin Information
(continued)
Table 1. T8532 Pin Descriptions
Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; I
u
indicates a pull-up
device is included on this lead, I
d
indicates a pull-down device is included on this lead.
Number
64, 8, 10, 18,
31, 39, 41, 49
1, 7, 11, 17, 32,
38, 42, 48
2, 6, 12, 16, 33,
37, 43, 47
3, 5, 13, 15, 34,
36, 44, 46
9, 19, 27, 30,
40, 50, 63
Name
VTX[7:0]
Type
AI
Name/Function
Analog Input.
Transmit signal voltage to be encoded.
VRTX[7:0]
AI
Transmit Reference Voltage.
2.4 V reference. Each pin must have a sep-
arate supply associated with the corresponding VTX pin.
Noninverting Receive Output.
This pin can drive high-impedance loads
either differentially or single ended. It is the complement of the VRN output.
Inverting Receive Output.
This pin can drive high-impedance loads either
differentially or single ended. It is the complement of the VRP output.
5 V Analog Power Supply.
Power supply decoupling capacitor (0.1
μ
F)
should be connected from each V
DDA
pin to analog ground. Capacitors
should be located as close as possible to the device pins.
Analog Ground.
VRP[7:0]
AO
VRN[7:0]
AO
V
DDA
—
4, 14, 21,
35, 45
51
V
SSA
—
V
DDD
—
5 V Digital Power Supply.
Decouple with a 0.1
μ
F capacitor to digital
ground.
Digital Ground.
Oversampled Transmit Data.
Four channels of 1.024 MHz
Σ
-
transmit
data is transmitted to the T8531 through each of these pins. The data rate
is 4.096 MHz.
Oversampled Receive Data.
Four channels of 1.024 MHz
Σ
-
receive
data is received from the T8531 on each of these pins. The data rate is
4.096 MHz.
Interface Clock.
The 4.096 MHz clock that enters this pin from the T8531
serves as the bit clock for all the oversampled data transmission between
this chip and the T8531. This is the master clock input for the T8532.
Interface Frame Sync.
This signal serves as the frame sync for the over-
sampled data interface between the T8532 and the T8531.
Control Data Interface Input.
The T8531 sends control register address
and data to the T8532 through this pin. One address byte and one data
byte are accepted each time CCS is toggled.
Control Data Interface Output.
Control register contents are clocked out
through this pin.
Control Interface Chip Select (Active-Low).
This active-low input
enables the control interface.
Reset (Active-Low).
This input must be pulled high for normal operation.
When pulled momentarily low (at least 1
μ
s) while OSCK is active, all pro-
grammable registers in the device are reset to the states specified under
powerup initialization. This pin has an internal pull-up resistor.
No Connect.
No connection to chip. These pins can be used as logic level
tie points.
62
V
SSD
—
CO
60, 59
OSDX[1:0]
61, 58
OSDR[1:0]
CI
57
OSCK
CI
56
OSFS
CI
54
CDI
CI
52
CDO
CO
53
CCS
CI
55
RSTB
TI
u
20, 22—26,
28, 29
NC
—
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相關(guān)代理商/技術(shù)參數(shù) |
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| T8531A | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8531A/8532 Multichannel Programmable Codec Chip Set |
| T8532 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8531A/8532 Multichannel Programmable Codec Chip Set |
| T8533 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8533/34 Quad Programmable Line Card Signal Processor |
| T85331G | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T85331J | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
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