參數(shù)資料
型號： TAS5036IPFCR
廠商： Texas Instruments, Inc.
英文描述： SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR
中文描述： 六聲道數(shù)字音頻PWM處理器
文件頁數(shù)： 14/49頁
文件大小： 642K
代理商： TAS5036IPFCR
Architecture Overview
9
SLES044B
—
November 2002
TAS5036
Table 2
–
2. Master and Slave Clock Modes
DESCRIPTION
M_S
DBSPD
XTL_IN
(MHz)
MCLK_IN
(MHz)
SCLK
(MHz)
LRCLK
(kHz)
MCLK_OUT
(MHz)#
Internal PLL, master, normal speed
1
0
8.192
-
2.048
32
8.192
Internal PLL, master, normal speed
1
0
11.2896
-
2.8224
44.1
11.2896
Internal PLL, master, normal speed
1
0
12.288
-
3.072
48
12.288
Internal PLL, master, double speed
1
1
-
22.5792
§
24.576
§
5.6448
88.2
22.5792
Internal PLL, master, double speed
1
1
-
6.144
96
24.576
Internal PLL, master, quad speed
1
0
-
22.5792
11.2896
176.4
22.5792
Internal PLL, master, quad speed
1
0
-
24.576
12.288
192
24.576
Internal PLL, slave, normal speed
0
0
-
8.192
§
11.2896
§
2.0484
32
Digital GND
Internal PLL, slave, normal speed
0
0
-
2.8224
44.1
Digital GND
Internal PLL, slave, normal speed
0
0
-
12.288
§
3.072
48
Digital GND
Internal PLL, slave, double speed
0
1
-
22.5792
5.6448
88.2
Digital GND
Internal PLL, slave, double speed
Internal PLL, slave, quad speed ||
Internal PLL, slave, quad speed ||
0
1
-
24.576
§
22.5792
§
6.144
96
Digital GND
0
0
-
11.2896
176
Digital GND
0
0
-
24.576
§
12.288
192
Digital GND
External PLL, master, normal speed
1
0
-
-
2.048
32
8.192
External PLL, master, normal speed
1
0
-
-
2.8224
44.1
11.2896
External PLL, master, normal speed
1
0
-
-
3.072
48
12.288
External PLL, master, double speed
1
1
-
-
5.6448
88.2
22.5792
External PLL, master, double speed
1
1
-
-
6.144
96
24.576
External PLL, master, quad speed
1
0
-
-
11.2896
176.4
22.5792
External PLL, master, quad speed
1
0
-
-
12.288
192
24.576
External PLL, slave, normal speed
0
0
-
8.192
§
11.2896
§
2.0484
32
Digital GND
External PLL, slave, normal speed
0
0
-
2.8224
44.1
Digital GND
External PLL, slave, normal speed
0
0
-
12.288
§
3.072
48
Digital GND
External PLL, slave, double speed
0
1
-
22.5792
5.6448
88.2
Digital GND
External PLL, slave, double speed
External PLL, slave, quad speed ||
External PLL, slave, quad speed ||
A crystal oscillator is connected to XTL_IN.
MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN_IN is provided.
§
External MCLK_IN connected to MCLK_IN_IN input
SCLK and LRCLK are outputs when M_S=1, and inputs when M_S=0.
#MCLK_OUT is driven low when M_S=0.
||Quad-speed mode is detected automatically.
SCLK can be 48 or 64 times Fs
0
1
-
24.576
§
22.5792
§
6.144
96
Digital GND
0
0
-
11.2896
176
Digital GND
0
0
-
24.576
§
12.288
192
Digital GND
Table 2
–
3. LRCLK, MCLK_IN, and External PLL Rates
NORMAL SPEED (kHz)
DOUBLE SPEED (kHz)
QUAD SPEED (kHz)
LRCLK
1FS
32
44.1
48
1FS
64
88.2
96
1FS
176.4
192
MCLK_IN
256FS
8,192
11,289.6
12,288
256FS
16,384
22,579.2
24,576
128FS
22,579.2
24,576
EXT. PLL
2048FS
65,536
90,316.8
98,304
1024FS
65,536
90,316.8
98,304
512FS
90,316.8
98,304
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