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參數(shù)資料
| 型號： | TDA8752BH |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Triple high-speed Analog-to-Digital Converter 110 Msps ADC |
| 中文描述： | 三高速模擬數(shù)字轉(zhuǎn)換器110 MSPS的ADC的 |
| 文件頁數(shù)： | 20/36頁 |
| 文件大小： | 154K |
| 代理商： | TDA8752BH |
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2000 Jan 10
20
Philips Semiconductors
Preliminary specification
Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)
TDA8752B
Table 8
Phase registers bits
The default programmed value is as follows:
No external clock: CKA at logic 0
No use of the second clock: CKB at logic 0
Phase shift for CKAO and CKADCO = 0
°
Phase shift for CKBO = 0
°
.
Clock CKao in pin CKAO = bit CKab = 0.
I
2
C-bus protocol
Table 9
I
2
C-bus address
The I
2
C-bus address of the circuit is 10011 xx0.
Bits A2 and A1 are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752Bs can be used on the same
system, using the addresses for ADD1 and ADD2 with the I
2
C-bus. The A0 bit must always be equal to logic 0 because
it is not possible to read the data in the register. The timing and protocol for the I
2
C-bus are standard. Two sequences
are available, see Tables 10 and 11.
Table 10
Address sequence for mode 0; note 1
Note
1.
Where: S = START condition, ACK = acknowledge and P = STOP condition.
Table 11
Address sequence for mode 1; note 1
Note
1.
Where: S = START condition, ACK = acknowledge and P = STOP condition.
Pa4 AND Pb4
Pa3 AND Pb3
Pa2 AND Pb2
Pa1 AND Pb1
Pa0 AND Pb0
PHASE SHIFT (
°
)
0
11.25
↓
↓
337.5
348.75
0
0
↓
↓
1
1
0
0
↓
↓
1
1
0
0
↓
↓
1
1
0
0
↓
↓
1
1
0
1
↓
↓
0
1
A7
A6
A5
A4
A3
A2
A1
A0
1
0
0
1
1
ADD2
ADD1
0
S
IC ADDRESS
ACK
SUBADDRESS
REGISTER1
ACK
DATA
REGISTER1
(see Table 1)
ACK
SUBADDRESS
REGISTER2
ACK
to
P
S
IC ADDRESS
ACK
SUBADDRESS
xxx1 1111
ACK
DATA
REGISTER1
(see Table 1)
ACK
DATA
REGISTER2
ACK
to
P
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