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參數(shù)資料
| 型號(hào)： | TDA8752BH |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Triple high-speed Analog-to-Digital Converter 110 Msps ADC |
| 中文描述： | 三高速模擬數(shù)字轉(zhuǎn)換器110 MSPS的ADC的 |
| 文件頁數(shù)： | 27/36頁 |
| 文件大?。?/td> | 154K |
| 代理商： | TDA8752BH |
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2000 Jan 10
27
Philips Semiconductors
Preliminary specification
Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)
TDA8752B
Notes
1.
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST
frequency). Conversion-to-noise ratio: S/N = EB
×
6.02 + 1.76 dB.
Output data acquisition is available after the maximum delay time t
d(o)
, which is the time during which the data is
available. All the timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then
be rechecked.
The I
2
C-bus timings are given for a frequency of 100 kbit/s (100 kHz). This bus can be used at a frequency of
400 kbit/s (400 kHz).
2.
3.
I
2
C-bus;
see note 3
f
SCL
t
BUF
clock frequency
0
100
kHz
time the bus must be free
before new transmission can
start
start condition hold time
4.7
μ
s
t
HD;STA
t
SU;STA
t
CKL
t
CKH
t
SU;DAT
t
HD;DAT
t
r
t
f
t
SU;STOP
C
L(bus)
4.0
μ
s
μ
s
μ
s
μ
s
start condition set-up time
repeated start
4.7
LOW-level clock period
4.7
HIGH-level clock period
4.0
data set-up time
250
ns
data hold time
0
ns
SDA and SCL rise time
for f
SCL
= 100 kHz
for f
SCL
= 100 kHz
1.0
μ
s
SDA and SCL fall time
300
ns
stop condition set-up time
4.0
μ
s
capacitive load for each bus
line
400
pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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| TDA8752BH/8 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple high-speed Analog-to-Digital Converter 110 Msps ADC |
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| TDA8752H/8 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple high speed Analog-to-Digital Converter ADC |
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