參數(shù)資料
型號(hào): TDA8752BH
廠商: NXP Semiconductors N.V.
英文描述: Triple high-speed Analog-to-Digital Converter 110 Msps ADC
中文描述: 三高速模擬數(shù)字轉(zhuǎn)換器110 MSPS的ADC的
文件頁(yè)數(shù): 23/36頁(yè)
文件大小: 154K
代理商: TDA8752BH
2000 Jan 10
23
Philips Semiconductors
Preliminary specification
Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)
TDA8752B
CHARACTERISTICS
V
CCA
= V11 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96 = 4.75 to 5.25 V; V
CCD
= V95 referenced
to DGND (V86) = 4.75 to 5.25 V; V
DDD
= V40 referenced to V
SSD
(V41) = 4.75 to 5.25 V; V
CCO
= V59
(or V69, V79 or V85) referenced to OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and V
SSD
short circuited together. T
amb
= 0 to 70
°
C; typical values measured at V
CCA
= V
DDD
= V
CCD
= V
CCO
= 5 V and
T
amb
= 25
°
C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
CCA
V
CCD
V
DDD
V
CCO
I
CCA
I
DDD
analog supply voltage
4.75
5.0
5.25
V
digital supply voltage
4.75
5.0
5.25
V
logic supply voltage
4.75
5.0
5.25
V
output stages supply voltage
4.75
5.0
5.25
V
analog supply current
120
mA
logic supply current for
I
2
C-bus and 3-wire
digital supply current
1.0
mA
I
CCD
I
CCO
I
CCO(PLL)
I
CCA(PLL)
V
CC
40
mA
output stages supply current
ramp input; f
CLK
= 110 MHz
26
mA
output PLL supply current
5
mA
analog PLL supply current
28
mA
supply voltage differences
V
CCA
V
CCD
V
CCO
V
CCD
; V
CCO
V
DDD
V
CCA
V
DDD
; V
CCD
V
DDD
V
CCA
V
CCO
total power consumption
0.25
0.25
0.25
0.25
+0.25
V
+0.25
V
+0.25
V
+0.25
V
P
tot
P
pd
ramp input; f
CLK
= 110 MHz
1.1
W
power consumption in
power-down mode
87
mW
R, G and B amplifiers
B
bandwidth
3 dB; T
amb
= 25
°
C
full-scale (black-to-white)
transition; input signal
settling time < 1 ns;
1 to 99%; T
amb
= 25
°
C
V
ref
= 2.5 V; minimum
coarse gain register;
code = 32; (see Fig.8)
maximum coarse gain
register; code = 99;
(see Fig.8)
250
MHz
t
set
settling time of the block ADC
plus AGC
4.5
6
ns
G
NCOARSE
coarse gain range
1.67
dB
8
dB
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