參數(shù)資料
型號(hào): TDA8752BH
廠商: NXP Semiconductors N.V.
英文描述: Triple high-speed Analog-to-Digital Converter 110 Msps ADC
中文描述: 三高速模擬數(shù)字轉(zhuǎn)換器110 MSPS的ADC的
文件頁數(shù): 24/36頁
文件大?。?/td> 154K
代理商: TDA8752BH
2000 Jan 10
24
Philips Semiconductors
Preliminary specification
Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)
TDA8752B
G
FINE
fine gain correction range
fine register input code = 0;
(see Fig.9)
fine register input code = 31;
(see Fig.9)
V
ref
= 2.5 V with 100 ppm/
°
C
maximum variation
0
dB
0.5
dB
G
amp
/T
amplifier gain stability as a
function of temperature
gain current
200
ppm/
°
C
I
GC
t
stab
±
20
μ
A
mdB/
μ
s
amplifier gain adjustment
speed
input voltage range
(peak-to-peak value)
input voltage rise time
HSYNC active; capacitors
on pins 8, 16 and 24 = 22 nF
corresponding to full-scale
output
f
i
= 110 MHz; square wave
f
i
= 110 MHz; square wave
maximum coarse gain;
T
amb
= 25
°
C
minimum coarse gain;
T
amb
= 25
°
C
25
V
i(p-p)
0.4
1.2
V
t
r(Vi)
t
f(Vi)
G
E(rms)
2.5
ns
input voltage fall time
2.5
ns
channel-to-channel gain
matching (RMS value)
1
%
2
%
Clamps
P
CLP
precision
black level noise on RGB
channels = 10 mV (max.)
(RMS value); T
amb
= 25
°
C
±
100 mV black level input
variation; clamp
capacitor = 4.7 nF
±
100 mV black level input
variation; clamp
capacitor = 4.7 nF
1
+1
LSB
t
COR1
clamp correction time to within
±
10 mV
300
ns
t
COR2
clamp correction time to less
than 1 LSB
10
lines
t
W(CLP)
CLP
E
clamp pulse width
500
2000
ns
channel-to-channel clamp
matching
code clamp reference
1
+1
LSB
A
off
clamp register input
code = 0
clamp register input
code = 255
clamp register input
code = 367
clamp register input
code = 398
63.5
LSB
64
LSB
120
LSB
136
LSB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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