參數(shù)資料
型號(hào)： TLV320ADC3001IYZHT
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16
封裝： GREEN, DSBGA-16
文件頁(yè)數(shù)： 6/81頁(yè)
文件大?。?/td> 836K
代理商： TLV320ADC3001IYZHT
SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
PLL START-UP
When the PLL is powered on, a start-up delay of approximately 10 ms occurs after the power-up command of the
PLL and before the clocks are available to the TLV320ADC3001. This delay is to ensure stable operation of the
PLL and clock-divider logic.
SOFTWARE POWER DOWN
By default, all circuit blocks are powered down following a reset condition. Hardware power up of each circuit
block can be controlled by writing to the appropriate control register. This approach allows the lowest
power-supply current for the functionality required. However, when a block is powered down, all of the register
settings are maintained as long as power is still being applied to the device.
miniDSP
The TLV320ADC3001 features a miniDSP core which is tightly coupled to the ADC. The fully programmable
algorithms for the miniDSP must be loaded into the device after power up. The miniDSP has direct access to the
digital stereo audio stream, offering the possibility for advanced, very low-group-delay DSP algorithms. The ADC
miniDSP has 512 programmable instructions, 256 data memory locations, and 128 programmable coefficients.
Software development for the TLV320ADC3001 is supported through TI's comprehensive PurePath
Studio
software development environment, a powerful, easy-to-use tool designed specifically to simplify software
development on Texas Instruments miniDSP audio platforms. The graphical development environment consists
of a library of common audio functions that can be dragged and dropped into an audio signal flow and graphically
connected together. The DSP code can then be assembled from the graphical signal flow with the click of a
mouse. See the TLV320ADC3001 product folder on www.ti.com to learn more about PurePath Studio software
and the latest status on available, ready-to-use DSP algorithms. PurePath Studio
DIGITAL INTERFACES
I2C CONTROL MODE
The TLV320ADC3001 supports the I2C control protocol using 7-bit addressing and is capable of operating in both
standard mode (
≤ 100 kHz) and fast mode (≤ 400 kHz). The device address is fixed with the value 0011 000.
I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving
them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver
contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of
a master. Some I2C devices can act as masters or slaves, but the TLV320ADC3001 can only act as a slave
device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted
across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate
level while SCL is LOW (a LOW on SDA indicates the bit is 0; a HIGH indicates the bit is 1). Once the SDA line
has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the receiver
shift register.
The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads
from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line.
Under normal circumstances, the master drives the clock line.
Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When
communication is taking place, the bus is active. Only master devices can start a communication. They do this by
causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock
line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its
counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from
HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.
14
Copyright
2008–2011, Texas Instruments Incorporated
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