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參數資料
| 型號： | TLV320ADC3001IYZHT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16 |
| 封裝： | GREEN, DSBGA-16 |
| 文件頁數： | 19/81頁 |
| 文件大小： | 836K |
| 代理商： | TLV320ADC3001IYZHT |
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SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
STEREO AUDIO ADC
The TLV320ADC3001 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times
oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8
kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC is in operation, the
device requires that an audio master clock be provided and appropriate audio clock generation be set up within
the device.
In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to
support the case where only mono record capability is required. In addition, both channels can be fully or partially
powered down.
The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an
initial sampling rate of 128 fS to the final output sampling rate of fS. The decimation filter provides a linear phase
output response with a group delay of 17/fS. The –3-dB bandwidth of the decimation filter extends to 0.45 fS and
scales with the sample rate (fS). The filter has minimum 73-dB attenuation over the stop band from 0.55 fS to 64
fS. Independent digital high-pass filters are also included with each ADC channel, with a corner frequency that
can be set independently by programmable coefficients or can be disabled entirely.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog anti-aliasing filtering are relaxed. The TLV320ADC3001 integrates a second-order
analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter,
provides sufficient anti-aliasing filtering without requiring additional external components.
The ADC is preceded by a programmable-gain amplifier (PGA), which allows analog gain control from 0 dB to 40
dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that only
changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on the
register programming (see register page 0 / register 81). This soft-stepping makes sure that volume control
changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on
power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the
gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled
by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the
device after the ADC power-down register is written to ensuree the soft-stepping to mute has completed. When
the ADC powerdown flag is no longer set, the audio master clock can be shut down.
AUDIO ANALOG INPUTS
Digital Volume Control
The TLV320ADC3001 also has a digital volume-control block with a range from
–12 dB to 20 dB in steps of 0.5
dB. It is set by programming page 0 / register 83 and page 0 / register 84 for left and right channels, respectively.
Table 2. Digital Volume Control for ADC
Left / Right Channel Page 0 /
Desired Gain
Register 83, Page 0 / Register 84,
dB
Bits D6
–D0
–12
110 1000
–11.5
110 1001
–11
110 1010
...
–0.5
111 1111
0
000 0000 (default)
0.5
000 0001
...
19.5
010 0111
20
010 1000
26
Copyright
2008–2011, Texas Instruments Incorporated
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| TLV320ADC3101 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Low Power Stereo ADC for Wireless Handsets and Portable Audio |
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