參數(shù)資料
型號: TLV320ADC3001IYZHT
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16
封裝: GREEN, DSBGA-16
文件頁數(shù): 17/81頁
文件大小: 836K
代理商: TLV320ADC3001IYZHT
SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
10 MHz
≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz
≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4
≤ J ≤ 11
R = 1
Example:
For MCLK = 12 MHz, fS = 44.1 kHz, NADC = 8, MADC = 2, and AOSR = 128:
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example:
For MCLK = 12 MHz, fS = 48 kHz , NADC = 8, MADC = 2, and AOSR = 128:
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
The following table lists several example cases of typical MCLK rates and how to program the PLL to achieve an
fS of 44.1 kHz or 48 kHz with NADC = 8, MADC = 2, and AOSR = 128.
fS = 44.1 kHz
MCLK (MHz)
P
R
J
D
ACHIEVED fS
% ERROR
2.8224
1
32
0
44100.00
0.0000
5.6448
1
16
0
44100.00
0.0000
12.0
1
7
5264
44100.00
0.0000
13.0
1
6
9474
44099.71
–0.0007
16.0
1
5
6448
44100.00
0.0000
19.2
1
4
7040
44100.00
0.0000
19.68
1
4
5893
44100.30
0.0007
48.0
4
1
7
5264
44100.00
0.0000
fS = 48 kHz
MCLK (MHz)
P
R
J
D
ACHIEVED fS
% ERROR
2.048
1
48
0
48000.00
0.0000
3.072
1
32
0
48000.00
0.0000
4.096
1
24
0
48000.00
0.0000
6.144
1
16
0
48000.00
0.0000
8.192
1
12
0
48000.00
0.0000
12.0
1
8
1920
48000.00
0.0000
13.0
1
7
5618
47999.71
–0.0006
16.0
1
6
1440
48000.00
0.0000
19.2
1
5
1200
48000.00
0.0000
19.68
1
4
9951
47999.79
–0.0004
48.0
4
1
8
1920
48000.00
0.0000
24
Copyright
2008–2011, Texas Instruments Incorporated
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