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參數(shù)資料
| 型號： | TLV320ADC3001IYZHT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16 |
| 封裝： | GREEN, DSBGA-16 |
| 文件頁數(shù)： | 16/81頁 |
| 文件大?。?/td> | 836K |
| 代理商： | TLV320ADC3001IYZHT |
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SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
AUDIO DATA CONVERTERS
The TLV320ADC3001 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at
different sampling rates in various combinations, which are described further as follows.
The TLV320ADC3001 supports a wide range of options for generating clocks for the ADC section as well as the
digital interface section and the other control blocks as shown in Figure 31. The clocks for the ADC require a
source reference clock. The clock can be provided on device pins MCLK and BCLK. The source reference clock
for the ADC section can be chosen by programming the ADC_CLKIN value on page 0 / register 4, bits D1
–D0.
The ADC_CLKIN can then be routed through highly flexible clock dividers shown in Figure 31 to generate various
clocks required for the ADC and programmable digital filter sections. In the event that the desired audio or
programmable digital filter clocks cannot be generated from the external reference clocks on MCLK and BCLK,
the TLV320ADC3001 also provides the option of using an on-chip PLL, which supports a wide range of fractional
multiplication values to generate the required system clocks. Starting from ADC_CLKIN, the TLV320ADC3001
provides for several programmable clock dividers to help achieve a variety of sampling rates for the ADC and the
clocks for the programmable digital filter section.
AUDIO CLOCK GENERATION
The audio converters in fully programmable filter mode in the TLV320ADC3001 need an internal audio master
clock at a frequency of
≥ N × fS, where N = IADC (page 0, register 21) when filter mode (page 0, register 61)
equals zero, otherwise N equals the instruction count from Table 6, ADC Processing Blocks. The master clock is
obtained from an external clock signal applied to the device.
The device can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a
programmable divider or a PLL, to get the proper internal audio master clock needed by the device. The BCLK
input can also be used to generate the internal audio master clock.
A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies
available in the system. This device includes a highly programmable PLL to accommodate such situations easily.
The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus
paid to the standard MCLK rates already widely used.
When the PLL is enabled,
fS = (PLLCLK_IN × K × R) / (NADC × MADC × AOSR × P), where
P = 1, 2, 3,
…, 8
R = 1, 2,
…, 16
K = J.D
J = 1, 2, 3,
…, 63
D = 0000, 0001, 0002, 0003,
…, 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by page 0, register 4, bits D3
–D2.
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of
precision).
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
512 kHz
≤ ( PLLCLK_IN / P ) ≤ 20 MHz
80 MHz
≤ (PLLCLK _IN × K × R / P ) ≤ 110 MHz
4
≤ J ≤ 55
When the PLL is enabled and D
≠ 0000, the following conditions must be satisfied to meet specified
performance:
Copyright
2008–2011, Texas Instruments Incorporated
23
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