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參數(shù)資料
| 型號(hào)： | TLV320AIC13I |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO30 |
| 封裝： | PLASTIC, SOP-30 |
| 文件頁數(shù)： | 10/55頁 |
| 文件大?。?/td> | 455K |
| 代理商： | TLV320AIC13I |
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3–5
3.4
IIR/FIR Control
3.4.1
Overflow Flags
The decimation IIR/FIR filter sets an overflow flag (bit D7) of control register 1 indicating that the input analog signal
has exceeded the range of internal decimation filter calculations. The interpolation IIR/FIR filter sets an overflow flag
(bit D4) of control register 1 indicating that the digital input has exceeded the range of internal interpolation filter
calculations. When the IIR/FIR overflow flag is set in the register, it remains set until the user reads the register.
Reading this value resets the overflow flag. These flags need to be reset after power-up by reading the register. If
FIR/IIR overflow occurs, the input signal is attenuated by either the PGA or some other method.
3.4.2
IIR/FIR Bypass Mode
An option is provided to bypass IIR/FIR filter sections of the decimation filter and the interpolation filter. This mode
is selected through bit D6 of control register 2 and effectively increases the frequency of the FS signal to four times
normal output rate of the IIR/FIR-filter. For example, for a normal sampling rate of 8 Ksps (i.e., FS = 8 kHz) with IIR/FIR,
if the IIR/FIR is bypassed, the frequency of FS is readjusted to 4
×8 kHz = 32 kHz. The sinc filters of the two paths
can not be bypassed. A maximum of eight devices in cascade can be supported in the IIR/FIR bypassed mode.
In this mode , the ADC channel outputs data which has been decimated only till 4 Fs. Similarly DAC channel input
needs to be pre-interpolated to 4 Fs before being given to the device. This mode allows users the flexibility to
implement their own filter in DSP for decimation and interpolation. M should be a multiple of 4 during IIR/FIR Bypass
mode.
3.5
System Reset and Power Management
3.5.1
Software and Hardware Reset
The TLV320AIC13 resets internal counters and registers in response to either of two events:
A low-going reset pulse is applied to terminal RESET
A 1 is written to the programmable software reset bits (D5 of control register 3)
NOTE:The TLV320AIC13 requires a power-up reset applied to the RESET pin.
Either event resets the control registers and clears all sequential circuits in the device. The H/W RESET (active low)
signal is at least 6 master clock periods long. As soon as the RESET input is applied, the TLV320AIC13 enters the
initialization cycle that lasts for 132 MCLKs, during which the DSPs serial port is put in 3-state. For a cascaded system
the rise time of H/W RESET needs to be less than the MCLK period and should satisfy setup time requirement of 2 ns
with respect to MCLK rise-edge. In stand-alone-slave mode SCLK must be running during RESET. RESET must be
synchronized with MCLK in all cases.
3.5.2
Power Management
Most of the device (all except the digital interface) enters the power-down mode when D7 and D6, in control register
3, are set to 1. When the PWRDN pin is low, the entire device is powered down. In either case, register contents are
preserved and the output of the amplifier is held at midpoint voltage to minimize pops and clicks.
The amount of power drawn during software power down is higher than during a hardware power down because of
the current required to keep the digital interface active. Additional differences between software and hardware
power-down modes are detailed in the following paragraphs.
3.5.2.1 Software Power-Down
Data bits D7 and D6 of control register 3 are used by TLV320AIC13 to turn on or off the software power-down mode,
which takes effect in the next frame FS. The ADC and DAC can be powered down individually. In the software
power-down, the digital interface circuit is still active while the internal ADC and DAC channel and differential outputs
OUTPx and OUTMx are disabled, and DOUT is put in 3-state in the data frame only. Register data in the control frame
is still accepted via DIN, but data in the data frame is ignored. The device returns to normal operation when D7 and
D6 of control register 3 are reset.
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| TLV320AIC13IDBTG4 | 功能描述:接口—CODEC Lo-Pwr Mono Voice Band CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC13IDBTR | 功能描述:接口—CODEC Lo-Pwr Mono Voice Band CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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