參數(shù)資料
型號： TLV320AIC13I
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO30
封裝： PLASTIC, SOP-30
文件頁數(shù)： 13/55頁
文件大小： 455K
代理商： TLV320AIC13I
3–7
SCLK
FS
DIN/DOUT
(16 Bit)
MSB
LSB
D15
D14
D1
D0
0
1
15
16
14
D15
16 SCLKs
Figure 3–6. Timing Diagram of FS
3.6.5
Cascade Mode and Frame-Sync Delayed (FSD)
In cascade mode, the DSP receives all frame-sync pulses from the master though the master’s FS. The master’s FSD
is output to the first slave and the first slave’s FSD is output to the second slave device and so on. Figure 3–8 shows
the cascade of 4 TLV320AIC13s in which the closest one to DSP is the master and the rest are slaves. The FSD output
of each device is input to the FS terminal of the succeeding device. Figure 3–9 shows the FSD timing sequence in
the cascade.
3.6.6
Stand-Alone Slave
In the stand-alone slave connection, the FS and SCLK are input in which they need to be synchronized to each other
and programmed according to Section 3.1 (Operating Frequencies). The FS and SCLK input are not required to
synchronize to the MCLK input but must remain active at all times to assure continuous sampling in the data converter.
FS is output for initial 132 MCLK and it must be kept low. DSP needs to keep FS low or high-impedance state for this
period to avoid contention on FS.
3.6.7
Asynchronous Sampling
(CODECs in cascade are sampled at different sampling frequency)
The AIC13s SMARTDM support different sampling frequency between the different codecs in cascade connecting
to a single to serial port in which all codecs is sampled at the same frequency of FS as followed. For example: fs1
and fs2 are desired sampling rates for CODEC1 and CODEC2 respectively:
1.
FS = MCLK/(16xMxNxP)
2.
FS = n1 x fs1 (n1 = 1,2, 0, 8 defined in the control register 3 of CODEC1)
3.
FS = n2 x fs2 (n2 = 1,2, 0, 8 defined in the control register 3 of CODEC2)
For validating the conversion data from this operation:
For DAC: DSP need to give same data for n1 samples. CODEC1 picks one of n1 samples.
For ADC: CODEC1 gives same data for n1 samples. DSP should pick one of n1 samples.
SCLK
FSD
(Output)
DIN/DOUT
(16 Bit)
MSB
LSB
D15
D14
D2
D1
0
1
14
15
13
D0
FS
16 SCLKs
D15
MSB
Figure 3–7. Timing Diagram for FSD Output
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