參數(shù)資料
型號: TLV320AIC3120IRHBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: AUDIO AMPLIFIER, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù): 137/150頁
文件大小: 1507K
代理商: TLV320AIC3120IRHBR
www.ti.com
SLAS653 – FEBRUARY 2010
Page 0 / Register 33 (0x21): Codec Secondary Interface Control 3
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Primary BCLK output = internally generated BCLK clock
1: Primary BCLK output = secondary BCLK
D6
R/W
0
0: Secondary BCLK output = primary BCLK
1: Secondary BCLK output = internally generated BCLK clock
D5–D4
R/W
00
00: Primary WCLK output = internally generated DAC_fS
01: Primary WCLK output = internally generated ADC_fS clock
10: Primary WCLK output = secondary WCLK
11: Reserved
D3–D2
R/W
00
00: Secondary WCLK output = primary WCLK
01: Secondary WCLK output = internally generated DAC_fS clock
10: Secondary WCLK output = internally generated ADC_fS clock
11: Reserved
D1
R/W
0
0: Primary DOUT = DOUT from codec serial-interface block
1: Primary DOUT = secondary DIN
D0
R/W
0
0: Secondary DOUT = primary DIN
1: Secondary DOUT = DOUT from codec serial interface block
Page 0 / Register 34 (0x22): I2C Bus Condition
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Reserved. Write only the reset value to these bits.
D5
R/W
0
0: I2C general-call address is ignored.
1: Device accepts I2C general-call address.
D4–D0
R/W
0 0000
Reserved. Write only zeros to these bits.
Page 0 / Register 35 (0x23): Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
XXXX XXXX
Reserved. Write only zeros to these bits.
Page 0 / Register 36 (0x24): ADC Flag Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R
1
0: ADC PGA applied gain
≠ programmed gain
1: ADC PGA applied gain = programmed gain
D6
R
0
0: ADC powered down
1: ADC powered up
D5(1)
R
0
0: AGC not saturated
1: AGC applied gain = maximum applicable gain by AGC
D4–D0
R
X XXXX
Reserved
(1)
Sticky flag bit. This is a read-only bit. It is automatically cleared once it is read and is set only if the source trigger occurs again.
Page 0 / Register 37 (0x25): DAC Flag Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R
0
0: DAC powered down
1: DAC powered up
D6
R
X
Reserved. Do not write to this bit.
D5
R
0
0: HPOUT driver powered down
1: HPOUT driver powered up
D4
R
0
0: Class-D driver powered down
1: Class-D driver powered up
D0–D3
R
XXXX
Reserved. Do not write to these bits.
Copyright 2010, Texas Instruments Incorporated
REGISTER MAP
87
Product Folder Link(s): TLV320AIC3120
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