參數(shù)資料
型號： TLV320AIC3120IRHBR
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： AUDIO AMPLIFIER, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 18/150頁
文件大?。?/td> 1507K
代理商： TLV320AIC3120IRHBR
SLAS653 – FEBRUARY 2010
www.ti.com
Table 6-5. Page 5 Registers (continued)
REGISTER
RESET
REGISTER NAME
NUMBER
VALUE
119 (0x77)
0000 0000
Coefficient C123(7:0) of ADC miniDSP
120 (0x78)
0000 0000
Coefficient C124(15:8) of ADC miniDSP
121 (0x79)
0000 0000
Coefficient C124(7:0) of ADC miniDSP
122 (0x7A)
0000 0000
Coefficient C125(15:8) of ADC miniDSP
123 (0x7B)
0000 0000
Coefficient C125(7:0) of ADC miniDSP
124 (0x7C)
0000 0000
Coefficient C126(15:8) of ADC miniDSP
125 (0x7D)
0000 0000
Coefficient C126(7:0) of ADC miniDSP
126 (0x7E)
0000 0000
Coefficient C127(15:8) of ADC miniDSP
127 (0x7F)
0000 0000
Coefficient C127(7:0) of ADC miniDSP
6.7
Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)
Default values shown for this page only become valid 100 ms following a hardware or software reset.
Page 8 / Register 0 (0x00): Page Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
Page 8 / Register 1 (0x01): DAC Coefficient RAM Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D4
R/W
0000
Reserved. Write only the reset value.
D3
R
0
DAC miniDSP generated flag for toggling MSB of coefficient RAM address (only used in non-adaptive
mode)
D2
R/W
0
DAC Adaptive Filtering Control
0: Adaptive filtering disabled in DAC miniDSP
1: Adaptive filtering enabled in DAC miniDSP
D1
R
0
DAC Adaptive Filter Buffer Control Flag
0: In adaptive filter mode, DAC miniDSP accesses DAC coefficient buffer A and the external control
interface accesses DAC coefficient buffer B.
1: In adaptive filter mode, DAC miniDSP accesses DAC coefficient buffer B and the external control
interface accesses DAC coefficient buffer A.
D0
R/W
0
DAC Adaptive Filter Buffer Switch Control
0: DAC coefficient buffers are not switched at the next frame boundary.
1: DAC coefficient buffers are switched at the next frame boundary, if adaptive filtering mode is enabled.
This bit self-clears on switching.
The remaining page-8 registers are either reserved registers or are used for setting coefficients for the
various filters in the TLV320AIC3111. Reserved registers should not be written to.
The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit
coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient
are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When
programming any coefficient value for a filter, the MSB register should always be written first, immediately
followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both
registers should be written in this sequence. Table 6-6 is a list of the page-8 registers, excepting the
previously described register 0.
114
REGISTER MAP
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3120
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