參數(shù)資料
型號： TLV320AIC3120IRHBR
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： AUDIO AMPLIFIER, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 119/150頁
文件大?。?/td> 1507K
代理商： TLV320AIC3120IRHBR
SLAS653 – FEBRUARY 2010
www.ti.com
NOTE
The TLV320AIC3102 has a mono DAC which inputs the mono data from the digital audio
data serial interface as the left channel, the right channel, or a mix of the left and right
channels of as [(L + R) ÷ 2] (page 0 / register 63, bits D5–D4).The TLV320AIC3120 has a
mono ADC which outputs the same data to both the left and right channels of the digital
audio data serial interface output. See Figure 1-1 for the signal flow of the DAC and ADC.
The audio bus of the TLV320AIC3120 can be configured for left- or right-justified, I2S, DSP, or TDM mode
of operation, where communication with standard telephony PCM interfaces is supported within the TDM
mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by
configuring page 0 / register 27, bits D5–D4. In addition, the word clock and bit clock can be
independently configured in either master or slave mode for flexible connectivity to a wide variety of
processors. The word clock is used to define the beginning of a frame, and may be programmed as either
a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected
ADC and DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in page 0 / register 30 (see Figure 5-33). The number of bit-clock pulses in a frame may need adjustment
to accommodate various word lengths as well as to support the case in which multiple TLV320AIC3120s
share the same audio bus.
The TLV320AIC3120 also includes a feature to offset the position of start of data transfer with respect to
the word clock. This offset can be controlled in terms of number of bit clocks and can be programmed in
page 0 / register 28.
The TLV320AIC3120 also has the feature of inverting the polarity of the bit clock used for transferring the
audio data as compared to the default clock polarity used. This feature can be used independently of the
mode of audio interface chosen. This can be configured via page 0 / register 29, bit D3.
The TLV320AIC3120 further includes programmability (page 0 / register 27, bit D0) to place the DOUT line
in the high-impedance state during all bit clocks when valid data is not being sent. By combining this
capability with the ability to program at what bit clock in a frame the audio data begins, time-division
multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on a single audio serial data
bus. When the audio serial data bus is powered down while configured in master mode, the pins
associated with the interface are put into a high-impedance output state.
By default, when the word clocks and bit clocks are generated by the TLV320AIC3120, these clocks are
active only when the codec (ADC, DAC, or both) are powered up within the device. This is done to save
power. However, it also supports a feature when both the word clocks and bit clocks can be active even
when the codec in the device is powered down. This is useful when using the TDM mode with multiple
codecs on the same bus, or when word clocks or bit clocks are used in the system as general-purpose
clocks.
5.8.1.1
Right-Justified Mode
The audio interface of the TLV320AIC3120 can be put into right-justified mode by programming page 0 /
register 27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the rising edge
of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid
on the rising edge of the bit clock preceding the rising edge of the word clock.
70
APPLICATION INFORMATION
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3120
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TLV320AIC3120IRHBT 功能描述:接口—CODEC Low-Pwr Audio CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC31EVM 功能描述:音頻 IC 開發(fā)工具 TLV320AIC31 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
TLV320AIC31EVM-PDK 功能描述:音頻 IC 開發(fā)工具 TLV320AIC31-PDK Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
TLV320AIC31IRHBR 功能描述:接口—CODEC Lo-Pwr Ster Codec for Port Aud/Teleph RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC31IRHBRG4 功能描述:接口—CODEC Lo-Pwr Ster Codec for Port Aud/Teleph RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
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