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參數(shù)資料
型號(hào)： TLV320AIC31IRHBTG4
廠商： Texas Instruments
文件頁數(shù)： 38/84頁
文件大小： 0K
描述： IC STEREO AUDIO CODEC LP 32-VQFN
標(biāo)準(zhǔn)包裝： 250
類型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
配用： 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
Page 0 / Register 12:
Audio Codec Digital Filter Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Left ADC High-pass Filter Control
00: Left ADC High-pass filter disabled
01: Left ADC High-pass filter –3-dB frequency = 0.0045 × ADC FS
10: Left ADC High-pass filter –3-dB frequency = 0.0125 × ADC FS
11: Left ADC High-pass filter –3-dB frequency = 0.025 × ADC FS
D5–D4
R/W
00
Right ADC High-pass Filter Control
00: Right ADC High-pass filter disabled
01: Right ADC High-pass filter –3-dB frequency = 0.0045 × ADC FS
10: Right ADC High-pass filter –3-dB frequency = 0.0125 × ADC FS
11: Right ADC High-pass filter –3-dB frequency = 0.025 × ADC FS
D3
R/W
0
Left DAC Digital Effects Filter Control
0: Left DAC digital effects filter disabled (bypassed)
1: Left DAC digital effects filter enabled
D2
R/W
0
Left DAC De-emphasis Filter Control
0: Left DAC de-emphasis filter disabled (bypassed)
1: Left DAC de-emphasis filter enabled
D1
R/W
0
Right DAC Digital Effects Filter Control
0: Right DAC digital effects filter disabled (bypassed)
1: Right DAC digital effects filter enabled
D0
R/W
0
Right DAC De-emphasis Filter Control
0: Right DAC de-emphasis filter disabled (bypassed)
1: Right DAC de-emphasis filter enabled
Page 0 / Register 13:
Reserved
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
00000000
Reserved. Write only '00000000' to this register.
Page 0 / Register 14:
Headset Configuration Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Driver Capacitive Coupling
0: Programs high-power outputs for capless driver configuration
1: Programs high-power outputs for ac-coupled driver configuration
D6(1)
R/W
0
Stereo Output Driver Configuration A
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo fully-differential output configuration is not being used
1: A stereo fully-differential output configuration is being used
D5–D4
R
00
Reserved. Write only '00' to these bits.
D3(1)
R/W
0
Stereo Output Driver Configuration B
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo pseudo-differential output configuration is not being used
1: A stereo pseudo-differential output configuration is being used
D2–D0
R
000
Reserved. Write only 0s to these bits.
(1)
Do not set D6 and D3 to 1 simultaneously
Page 0 / Register 15:
Left ADC PGA Gain Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
1
Left ADC PGA Mute
0: The left ADC PGA is not muted
1: The left ADC PGA is muted
Copyright 2006–2008, Texas Instruments Incorporated
43
Product Folder Link(s): TLV320AIC31
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