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參數(shù)資料
型號(hào)： TLV320AIC31IRHBTG4
廠商： Texas Instruments
文件頁(yè)數(shù)： 44/84頁(yè)
文件大小： 0K
描述： IC STEREO AUDIO CODEC LP 32-VQFN
標(biāo)準(zhǔn)包裝： 250
類型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
配用： 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
Page 0 / Register 28:
Left AGC Control Register C
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Noise Gate Hysteresis Level Control
00: Hysteresis is disabled
01: Hysteresis = 1-dB
10: Hysteresis = 2-dB
11: Hysteresis = 4-dB
D5–D1
R/W
00000
Left AGC Noise Threshold Control
00000: Left AGC Noise/Silence Detection disabled
00001: Left AGC noise threshold = –30-dB
00010: Left AGC noise threshold = –32-dB
00011: Left AGC noise threshold = –34-dB
…
11101: Left AGC noise threshold = –86-dB
11110: Left AGC noise threshold = –88-dB
11111: Left AGC noise threshold = –90-dB
D0
R/W
0
Left AGC Clip Stepping Control
0: Left AGC clip stepping disabled
1: Left AGC clip stepping enabled
Page 0 / Register 29:
Right AGC Control Register A
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Right AGC Enable
0: Right AGC is disabled
1: Right AGC is enabled
D6-D4
R/W
000
Right AGC Target Gain
000: Right AGC target gain = –5.5-dB
001: Right AGC target gain = –8-dB
010: Right AGC target gain = –10-dB
011: Right AGC target gain = –12-dB
100: Right AGC target gain = –14-dB
101: Right AGC target gain = –17-dB
110: Right AGC target gain = –20-dB
111: Right AGC target gain = –24-dB
D3–D2
R/W
00
Right AGC Attack Time
These time constants will not be accurate when double rate audio mode is enabled.
00: Right AGC attack time = 8-msec
01: Right AGC attack time = 11-msec
10: Right AGC attack time = 16-msec
11: Right AGC attack time = 20-msec
D1–D0
R/W
00
Right AGC Decay Time
These time constants will not be accurate when double rate audio mode is enabled.
00: Right AGC decay time = 100-msec
01: Right AGC decay time = 200-msec
10: Right AGC decay time = 400-msec
11: Right AGC decay time = 500-msec
Page 0 / Register 30:
Right AGC Control Register B
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D1
R/W
1111111
Right AGC Maximum Gain Allowed
0000000: Maximum gain = 0.0-dB
0000001: Maximum gain = 0.5-dB
0000010: Maximum gain = 1.0-dB
…
1110110: Maximum gain = 59.0-dB
1110111–111111: Maximum gain = 59.5-dB
D0
R/W
0
Reserved. Write only '0' to this register bit.
Copyright 2006–2008, Texas Instruments Incorporated
49
Product Folder Link(s): TLV320AIC31
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