SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ..................................................." />
參數(shù)資料
型號： TLV320AIC31IRHBTG4
廠商： Texas Instruments
文件頁數(shù)： 50/84頁
文件大?。?/td> 0K
描述： IC STEREO AUDIO CODEC LP 32-VQFN
標(biāo)準(zhǔn)包裝： 250
類型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
配用： 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com
Page 0 / Register 41:
DAC Output Switching Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Left DAC Output Switching Control
00: Left DAC output selects DAC_L1 path
01: Left DAC output selects DAC_L3 path to left line output driver
10: Left DAC output selects DAC_L2 path to left high-power output drivers (1)
11: Reserved. Do not write this sequence to these register bits.
D5–D4
R/W
00
Right DAC Output Switching Control
00: Right DAC output selects DAC_R1 path
01: Right DAC output selects DAC_R3 path to right line output driver
10: Right DAC output selects DAC_R2 path to right high-power output drivers (1)
11: Reserved. Do not write this sequence to these register bits.
D3–D2
R/W
00
Reserved. Write only '0's to these bits.
D1–D0
R/W
00
DAC Digital Volume Control Functionality
00: Left and right DAC channels have independent volume controls
01: Left DAC volume follows the right channel control register
10: Right DAC volume follows the left channel control register
11: Left and right DAC channels have independent volume controls (same as 00)
(1)
When using the DAC direct paths (DAC_L2 and DAC_R2), the signal will be gained up by a factor of –1 dB.
Page 0 / Register 42:
Output Driver Pop Reduction Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D4
R/W
0000
Output Driver Power-On Delay Control
0000: Driver power-on time = 0-
sec
0001: Driver power-on time = 10-
sec
0010: Driver power-on time = 100-
sec
0011: Driver power-on time = 1-msec
0100: Driver power-on time = 10-msec
0101: Driver power-on time = 50-msec
0110: Driver power-on time = 100-msec
0111: Driver power-on time = 200-msec
1000: Driver power-on time = 400-msec
1001: Driver power-on time = 800-msec
1010: Driver power-on time = 2-sec
1011: Driver power-on time = 4-sec
1100–1111: Reserved. Do not write these sequences to these register bits.
D3-D2
R/W
00
Driver Ramp-up Step Timing Control
00: Driver ramp-up step time = 0-msec
01: Driver ramp-up step time = 1-msec
10: Driver ramp-up step time = 2-msec
11: Driver ramp-up step time = 4-msec
D1
R/W
0
Weak Output Common-mode Voltage Control
0:
Weakly driven output common-mode voltage is generated from bandgap reference
1:
Weakly driven output common-mode voltage is generated from resistor divider off the AVDD
supply
D0
R/W
0
Reserved. Write only '0' to this register bit.
54
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC31
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