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參數(shù)資料
| 型號(hào)： | TMP89FH42UG |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, LQFP-44 |
| 文件頁(yè)數(shù)： | 115/317頁(yè) |
| 文件大?。?/td> | 6434K |
| 代理商： | TMP89FH42UG |
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14.4 Functions
Timer counters TC00 and TC01 have 8-bit modes in which they are used independently and 16-bit modes in which
they are cascaded.
The 8-bit modes include four operation modes; the 8-bit timer mode, the 8-bit event counter mode, the 8-bit pulse
width modulation output (PWM) mode and the 8-bit programmable pulse generated output (PPG) mode.
The 16-bit modes include four operation modes; the 16-bit timer mode, the 16-bit event counter mode, the 12-bit
PWM mode and the 16-bit PPG mode.
14.4.1
8-bit timer mode
In the 8-bit timer mode, the up-counter counts up using the internal clock, and interrupts can be generated
regularly at specified times. The operation of TC00 is described below, and the same applies to the operation of
TC01. (Replace TC00- by TC01-).
14.4.1.1
Setting
TC00 is put into the 8-bit timer mode by setting T00MOD<TCM0> to "00" or "01", T001CR<TCAS> to
"0" and T00MOD<EIN0> to "0". Select the source clock at T00MOD<TCK0>. Set the count value to be used
for the match detection as an 8-bit value at the timer register T00REG.
Set T00MOD<DBE0> to "1" to use the double buffer.
Setting T001CR<T00RUN> to "1" starts the operation. After the timer is started, writing to T00MOD
becomes invalid. Be sure to complete the required mode settings before starting the timer.
14.4.1.2
Operation
Setting T001CR<T00RUN> to "1" allows the 8-bit up counter to increment based on the selected internal
source clock. When a match between the up counter value and the T00REG set value is detected, an INTTC00
interrupt request is generated and the up counter is cleared to "0x00". After being cleared, the up counter
restarts counting. Setting T001CR<T00RUN> to "0" during the timer operation makes the up counter stop
counting and be cleared to "0x00".
14.4.1.3
Double buffer
The double buffer can be used for T00REG by setting T00MOD<DBE0>. The double buffer is disabled
by setting T00MOD<DBE0> to "0" or enabled by setting T00MOD<DBE0> to "1".
·
When the double buffer is enabled
When a write instruction is executed on T00REG during the timer operation, the set value is
initially stored in the double buffer, and T00REG is not immediately updated. T00REG compares
the previous set value with the up counter value. When the values match, an INTTC00 interrupt
request is generated and the double buffer set value is stored in T00REG. Subsequently, the match
detection is executed using a new set value.
When a write instruction is executed on T00REG while the timer is stopped, the set value is
immediately stored in both the double buffer and T00REG.
·
When the double buffer is disabled
When a write instruction is executed on T00REG during the timer operation, the set value is
immediately stored in T00REG. Subsequently, the match detection is executed using a new set
value.
If the value set to T00REG is smaller than the up counter value, the match detection is executed
using a new set value after the up counter overflows. Therefore, the interrupt request interval may
TMP89FH42
Page 185
RA004
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