參數(shù)資料
型號(hào)： TMP89FH42UG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, LQFP-44
文件頁(yè)數(shù)： 301/317頁(yè)
文件大?。?/td> 6434K
代理商： TMP89FH42UG
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Table 4-1 External Interrupts
Source
Pin
Enable conditions
Interrupt request sig-
nal generated at
External interrupt pin input signal width and noise removal
NORMAL1/2, IDLE1/2
SLOW1/2, SLEEP1
INT0
IMF AND EF16 = 1 Falling edge
Less than 1/fcgck: Noise
More than 1/fcgck and less than 2/fcgck:
Indeterminate
More than 2/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Inde-
terminate
More than 8/fs: Signal
INT1
IMF AND EF17 = 1
Falling edge
Rising edge
Both edges
Less than 2/fspl: Noise
More than 2/fspl and less than 3/fspl+1/
fcgck: Indeterminate
More than 3/fspl+1/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Inde-
terminate
More than 8/fs: Signal
INT2
IMF AND EF18 = 1
Falling edge
Rising edge
Both edges
Less than 2/fspl: Noise
More than 2/fspl and less than 3/fspl+1/
fcgck: Indeterminate
More than 3/fspl+1/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Inde-
terminate
More than 8/fs: Signal
INT3
IMF AND EF19 = 1
Falling edge
Rising edge
Both edges
Less than 2/fspl: Noise
More than 2/fspl and less than 3/fspl+1/
fcgck: Indeterminate
More than 3/fspl+1/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Inde-
terminate
More than 8/fs: Signal
INT4
IMF AND EF20 = 1
Falling edge
Rising edge
Both edges
"H" level
Less than 2/fspl: Noise
More than 2/fspl and less than 3/fspl+1/
fcgck: Indeterminate
More than 3/fspl+1/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Inde-
terminate
More than 8/fs: Signal
INT5
IMF AND EF8 = 1
Falling edge
Less than 1/fcgck: Noise
More than 1/fcgck and less than 2/fcgck:
Indeterminate
More than 2/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Inde-
terminate
More than 8/fs: Signal
Note 1: fcgck, Gear clock [Hz]; fs, low frequency clock [Hz]; fspl, Sampling interval [Hz]
4.3.1
Low power consumption function
External interrupts have a function that saves power by using the low power consumption register (POFFCR3)
when they are not used.
Setting POFFCR3<INTxEN> to "0" stops (disables) the basic clock for external interrupts and helps save
power. Note that this makes external interrupts unavailable. Setting POFFCR3<INTxEN> to "1" supplies (ena-
bles) the basic clock for external interrupts and makes external interrupts available.
After reset, POFFCR3<INTxEN> is initialized to "0" and external interrupts become unavailable. When using
the external interrupt function for the first time, be sure to set POFFCR3<INTxEN> to "1" in the initial setting
of software (before operating the external interrupt control registers).
Note:Interrupt request signals may be generated when INTxEN is changed. Before changing INTxEN, clear
the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the oper-
ation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the
operation mode is changed and clear the interrupt latch. And when the operation mode is changed from
SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is
changed and clear the interrupt latch.
4.3.2
External interrupt 0
External interrupt 0 detects the falling edge of the INT0 pin and generates interrupt request signals.
In NORMAL1/2 or IDLE1/2 mode, pulses of less than 1/fcgck are removed as noise and pulses of 2/fcgck or
more are recognized as signals.
In SLOW/SLEEP mode, pulses of less than 4/fs are removed as noise and pulses of 8/fs or more are recognized
as signals.
TMP89FH42
4. External Interrupt control circuit
4.3 Function
Page 68
RA000
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