參數(shù)資料
型號: TMP90CM38
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit A/D,D/A Converter,RAM,ROM,General Serial Interface,Multifuction Timer/Event Counter,Signal Selector Circuit,PWM Output(高速、先進的 CMOS 8位微控制器(芯片集成了8位A/D,D/A轉(zhuǎn)換器,ROM,RAM,通用串行接口,多功能定時器/事件計數(shù)器,信號選擇電路,PWM輸出))
中文描述: 采用先進的CMOS高速8位微控制器,集成8位A / D,D / A轉(zhuǎn)換,內(nèi)存,光盤,通用串行接口,Multifuction定時器/事件計數(shù)器,信號選擇器電路,PWM輸出(高速,先進的的CMOS 8位微控制器(芯片集成了8位A / D轉(zhuǎn)換,數(shù)/模轉(zhuǎn)換器,ROM和RAM內(nèi)存,通用串行接口,多功能定時器/事件計數(shù)器,信號選擇電路,脈寬調(diào)制輸出))
文件頁數(shù): 122/172頁
文件大?。?/td> 5946K
代理商: TMP90CM38
122
TOSHIBA CORPORATION
TMP90CM38
Table 3.9 (2) Selection of Transfer Rate (2) (When Timer 0 (Input Clock T1) is Used)) Unit: Kbps
fc
12.288
MHz
12
MHz
9.8304
MHz
8
MHz
6.144
MHz
TREG2
1H
96
76.8
62.5
48
2H
48
38.4
31.25
24
3H
32
31.25
16
4H
24
19.2
12
5H
19.2
9.6
8H
12
9.6
6
AH
9.6
4.8
10H
6
4.8
3
14H
4.8
2.4
How to calculate the transfer rate (when timer 2 is used0)
Input clock of timer 2
T1 = fc/8
T4 = fc/32
T16 = fc/128
Serial clock generation circuit
This circuit generates the basic clock for transmitting
and receiving data.
1) I/O interface mode
When in SCLK1 output mode with the setting of
SCCR1 <IOC1> = “0”, the basic clock will be gener-
ated by dividing by 2 the output of the baud rate gen-
erator described before. When in SCLK1 input mode
with the setting of SCCR1 <IOC1> = “1”, the rising
edge or the falling edge will be detected according to
the setting of SCCR1 <SCLK1> register to generate
the basic clock.
2) Asynchronous communication (UART) mode
According to the setting of SCMOD1 <SC11,01>, the
above baud rate generator clock, internal clock 1 (fc/
2) (312.5 Kbaud at 10MHz), or the match detect signal
from timer 2 will be selected to generate the basic clock
SIOCK.
Receiving counter
The receiving counter is a 4-bit binary counter used in
asynchronous communication (UART) mode and
counts up by SIOCLK1 clock. 16 pulses of SIOCLK1
are used for receiving 1 bit of data, and the data is
sampled three times at the 7th, 8th and 9th clock.
With the three samples, the received data is evaluated
by the rule of majority.
For example, if the sampled data is “1”, “0” and “1” at
7th, 8th and 9th clock, respectively, the received data
is evaluated as “1”. The sampled data “0”, “0”, and “1”
is evaluated that the received data is “0”.
Receiving control
1) I/O interface mode
When in SCLK1 output mode with the setting of
SCCR1 <IOC1> = “0”, RxD1 signal will be sampled at
the rising edge of shift clock which is output to SCLK
pin.
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