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參數(shù)資料
| 型號： | TMP90CM38 |
| 廠商： | Toshiba Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit A/D,D/A Converter,RAM，ROM，General Serial Interface,Multifuction Timer/Event Counter，Signal Selector Circuit,PWM Output(高速、先進(jìn)的 CMOS 8位微控制器（芯片集成了8位A/D，D/A轉(zhuǎn)換器,ROM，RAM，通用串行接口，多功能定時器/事件計數(shù)器,信號選擇電路，PWM輸出）) |
| 中文描述： | 采用先進(jìn)的CMOS高速8位微控制器，集成8位A / D，D / A轉(zhuǎn)換，內(nèi)存，光盤，通用串行接口，Multifuction定時器/事件計數(shù)器，信號選擇器電路，PWM輸出（高速，先進(jìn)的的CMOS 8位微控制器（芯片集成了8位A / D轉(zhuǎn)換，數(shù)/模轉(zhuǎn)換器，ROM和RAM內(nèi)存，通用串行接口，多功能定時器/事件計數(shù)器，信號選擇電路，脈寬調(diào)制輸出）） |
| 文件頁數(shù)： | 125/172頁 |
| 文件大?。?/td> | 5946K |
| 代理商： | TMP90CM38 |
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TOSHIBA CORPORATION
125
TMP90CM38
Transmission buffer
Transmission buffer SCBUF1 shifts out and sends the
transmission data written from the CPU from the least
significant bit (LSB) in order, using transmission shift
clock TxDSFT1 which is generated by the transmission
control. When all bits are shifted out, the transmission
buffer becomes empty and generates INTTX1 interrupt.
Parity control circuit
When serial channel control register SCCR1 <PE1> is
set to “1” , it is possible to transmit and receive data
with parity. However, parity can be added only in 7-bit
UART or 8-bit UART mode. With SCCR1 <EVEN1>
register, even (odd) parity can be selected.
For transmission, parity is automatically generated
according to the data written in the transmission buffer
SCBUF, and data are transmitted after being stored in
SCBUF1 <TB71> when in 7-bit UART mode while in
SCMOD1 <TB81> in 8-bit UART mode. <PE1> and
<EVEN1 > must be set before transmission data are
written in the transmission buffer.
For receiving, data are shifted in the receiving buffer 1,
and parity is added after the data are transferred in the
receiving buffer 2 (SCBUF1), and then compared with
<RB71> of SCBUF1 when in 7-bit UART mode and
with SCCR1 <RB81> when in 8-bit UART mode. If
they are not equal, a parity error occurs, and SCCR1
<PERR1> flag is set.
Error flag
Three error flags are provided to increase the reliability
of receiving data.
1) Overrun error (SCCR1 <OERR1>)
If all bits of the next data are received in receiving buffer
1 while valid data are still stored in receiving buffer 2
(SCBUF1), an overrun error will occur.
2) Parity error (SCCR1 <PERR1>)
The parity generated for the data shifted in receiving
buffer 2 (SCBUF1) is compared with the parity bit
received from the RxD1 pin. If they are not equal, a
parity error occurs.
3) Framing error (SCCR1 <FERR1>)
The stop bit of received data is sampled three times
around the center. If the majority results is “0”, a fram-
ing error occurs.
11
Generation Timing
1) UART mode
Note:
Framing error occurs after an interrupt has occurred. Therefore, to
check for framing error during interrupt operation, it is necessary to
wait for 1 bit period of time.
Receiving
Mode
9 Bit
8 Bit + Parity
8 Bit, 7 Bit + Parity,
7 Bit
Interrupt timing
Center of last bit
(Bit 8)
Center of last bit
(Parity Bit)
Center of stop bit
Framing error
timing
Center of stop bit
Center of stop bit
Center of stop bit
Parity error timing
Center of last bit
(Bit 8)
Center of last bit
(Parity Bit)
Center of stop bit
Over-run error
timing
Center of last bit
(Bit 8)
Center of last bit
(Parity Bit)
Center of stop bit
Transmitting
Mode
9 Bit
8 Bit + Parity
8 Bit, 7 Bit + Parity,
7 Bit
Interrupt timing
Just before last
bits transmitted
←
←
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相關(guān)代理商/技術(shù)參數(shù) |
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| TMP90CM38F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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| TMP90CM39T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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