參數(shù)資料
型號: TMP90CM38
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit A/D,D/A Converter,RAM,ROM,General Serial Interface,Multifuction Timer/Event Counter,Signal Selector Circuit,PWM Output(高速、先進的 CMOS 8位微控制器(芯片集成了8位A/D,D/A轉(zhuǎn)換器,ROM,RAM,通用串行接口,多功能定時器/事件計數(shù)器,信號選擇電路,PWM輸出))
中文描述: 采用先進的CMOS高速8位微控制器,集成8位A / D,D / A轉(zhuǎn)換,內(nèi)存,光盤,通用串行接口,Multifuction定時器/事件計數(shù)器,信號選擇器電路,PWM輸出(高速,先進的的CMOS 8位微控制器(芯片集成了8位A / D轉(zhuǎn)換,數(shù)/模轉(zhuǎn)換器,ROM和RAM內(nèi)存,通用串行接口,多功能定時器/事件計數(shù)器,信號選擇電路,脈寬調(diào)制輸出))
文件頁數(shù): 149/172頁
文件大小: 5946K
代理商: TMP90CM38
TOSHIBA CORPORATION
149
TMP90CM38
The watchdog timer is a 22-stage binary counter that
uses (fc/2) as the input clock.
The binary counter outputs are 2
2
/fc. One of these outputs is used for watchdog timer output
WDTOUT.
WDTOUT outputs “0” to reset the peripheral devices
16
/fc, 2
18
/fc, 2
20
/fc and
22
when the watchdog timer overflows.
WDTOUT also is connected to RESET inside the
WDTOUT TMP90CM38. In this case, WDTOUT outputs “0” in
a 32/fxtal = 2.0
μ
sec (fxtal = 16MHz) cycle and simultaneously
resets the TMP90CM38.
3.11.2 Control Registers
The watchdog timer (WDT) is controlled by two control registers
(WDMODE and WDCR).
(1)
Watchdog Timer Mode Register (WDMOD
Watchdog timer detection time setting (WDTP)
This is a 2-bit flag used to set the watchdog timer
interrupt time for looping (runaway) detection. This flag
is initialized to WDMOD <WDTP0, 1> = 00 by resets,
which results in a value of 216/fc [sec]. (The number of
states is approximately 32,768.)
Watchdog timer enable/disable control (WDTE)
This bit is initialized to WDTE = 1 by resets, which
enables the watchdog timer.
To disable the watchdog timer, it is only necessary to
clear this bit to “0” and write the disable code (B1H) to the
WDCR register. It is difficult for the watchdog timer to be
disabled by looping.
To disable the watchdog timer after it has been enabled,
it is only necessary to write “1” to the <WDTE> bit.
Watchdog timer out reset connection (RESCR)
This flag is used to set whether or not the
TMP90CM38 will be reset when looping is detected
and whether or not to output WDTOUT.
<RESCR> is set to “1” by reset operations; therefore,
P80 is set as the WDTOUT pin and connected internally to
the RESET pin.
P80 can be set as either the WDTOUT pin or port pin
by overwriting <RESCR>. However, caution is required
because a redundant structure is used to prevent misop-
eration. The <RESCR> bit is linked to the P38CR
<WDTOUTC> therefore, it is always necessary to write
“1” the <WDTOUTC> when the <RESCR> bit is over-
written.
The <RESCR> bit is set only after “1” is written to the
<WDTOUTC> and then either “0” or “1” is written to
the RESCR bit.
Writing to the <RESCR> bit automatically clears the
<WDTOUTC> to “0”; therefore, when resetting the
<RESCR> bit, again write “1” to the <WDTOUTC>.
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