參數(shù)資料
型號: TMP90CM38
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit A/D,D/A Converter,RAM,ROM,General Serial Interface,Multifuction Timer/Event Counter,Signal Selector Circuit,PWM Output(高速、先進(jìn)的 CMOS 8位微控制器(芯片集成了8位A/D,D/A轉(zhuǎn)換器,ROM,RAM,通用串行接口,多功能定時器/事件計數(shù)器,信號選擇電路,PWM輸出))
中文描述: 采用先進(jìn)的CMOS高速8位微控制器,集成8位A / D,D / A轉(zhuǎn)換,內(nèi)存,光盤,通用串行接口,Multifuction定時器/事件計數(shù)器,信號選擇器電路,PWM輸出(高速,先進(jìn)的的CMOS 8位微控制器(芯片集成了8位A / D轉(zhuǎn)換,數(shù)/模轉(zhuǎn)換器,ROM和RAM內(nèi)存,通用串行接口,多功能定時器/事件計數(shù)器,信號選擇電路,脈寬調(diào)制輸出))
文件頁數(shù): 80/172頁
文件大?。?/td> 5946K
代理商: TMP90CM38
80
TOSHIBA CORPORATION
TMP90CM38
Table 3.6 (2) 16-bit Timer (Interrupt) Cycle and Input Clock
Interrupt cycle
(at fc = 16MHz)
Resolution
Input clock
0.5
2
μ
8
μ
μ
s ~ 131.072ms
s ~ 524.288ms
s ~ 32.768ms
0.5
2
8
μ
s
s
s
T1 (8/fc)
T16 (32/fc)
T256 (128/fc)
μ
μ
The lower 8 bits of the timer (interrupt) cycle are set by
the timer register TREG0, and the upper 8 bits are set
by TREG1. Note that TREG0 always must be set first.
(Writing data into TREG0 disables the comparator
temporarily, and the comparator is restarted by writing
data into TREG1.)
Setting example: To generate interrupt INTT1 every
0.5 seconds at fc = 16MHz, set the
following values for timer registers
TREG0 and TREG1.
When counting by using T16
(8
μ
s @16MHz),
0.5s
F424H
Therefore, set TREG1 = F4H and
TREG0 = 24H, respectively.
÷
8
μ
s = 62500 =
The comparator match signal is output from timer 0 each
time the up-counter matches UC0, where the up-counter UC0
is not cleared.
With the timer 1 comparator, the match detect signal is
output at each comparator timing when up-counter UC1 and
TREG1 values match. When the match detect signal is output
simultaneously from both comparators of timer 0 and timer 1,
the up-counters UC0 and UC1 are cleared to “0”, and the
interrupt INTT1 is generated. If inversion is enabled, the value
of the timer flip-flop TFF1 is inverted.
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