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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346C–JANUARY 2007–REVISED NOVEMBER 2007
Table 2-15. EMAC (MII/RMII) and MDIO Terminal Functions
SIGNAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
EMAC (MII)
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
HCNTL1/MTXEN/
GP[75]
HD15/MTXCLK/
GP[73]
HD9/MCOL/
GP[67]
HD11/MTXD3/
GP[69]
HD12/MTXD2/
GP[70]
HD13/MTXD1/
GP[71]
HD14/MTXD0/
GP[72]
HR/W/MRXCLK/
GP[77]
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Enable output MTXEN.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Clock input MTXCLK.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Collision Detect input MCOL.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 3 output MTXD3.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 2 output MTXD2.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 1 output MTXD1.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 0 output MTXD0.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Clock input MRXCLK.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data Valid input
MRXDV.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Error input MRXER.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Carrier Sense input MCRS.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data 3 input MRXD3.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data 2 input MRXD2.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive data 1 input MRXD1.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data 0 input MRXD0.
D3
C4
I/O/Z
A4
A4
I/O/Z
C6
C6
I/O/Z
C5
A5
I/O/Z
D5
C5
I/O/Z
B4
B4
I/O/Z
D4
B5
I/O/Z
A3
A3
I/O/Z
HHWIL/MRXDV/
GP[74]
IPD
DV
DD33
C4
D3
I/O/Z
HCNTL0/MRXER/
GP[76]
HD10/MCRS/
GP[68]
HINT/MRXD3/
GP[82]
HRDY/MRXD2/
GP[80]
HDS1/MRXD1/
GP[79]
HDS2/MRXD0/
GP[78]
IPD
DV
DD33
IPD
DV
DD33
IPU
DV
DD33
IPU
DV
DD33
IPU
DV
DD33
IPU
DV
DD33
B3
B2
I/O/Z
B5
B6
I/O/Z
C2
D2
I/O/Z
D2
C3
I/O/Z
B2
B3
I/O/Z
C3
C2
I/O/Z
EMAC (RMII)
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC carrier sense/receive
data valid (RMCRSDV)
[I]
.
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC receive error (RMRXER)
[I]
.
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC transmit data pin 1
(RMTXD1)
[O/Z]
.
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC transmit data pin 0
(RMTXD0)
[O/Z]
.
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC RMII reference clock
(RMREFCLK)
[I]
.
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC transmit enable
(RMTXEN)
[O/Z]
.
IPD
DV
DD33
RMCRSDV/GP[30]
G19
K22
I/O/Z
IPD
DV
DD33
RMRXER/GP[52]
A15
A19
I/O/Z
RMTXD1/GP[27]/
(LENDIAN)
IPU
DV
DD33
H17
L19
I/O/Z
IPD
DV
DD33
RMTXD0/GP[28]
H16
J21
I/O/Z
IPD
DV
DD33
RMREFCLK/GP[31]
D19
G22
I/O/Z
IPD
DV
DD33
RMTXEN/GP[29]
H15
K21
I/O/Z
(1)
(2)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see
Section 3.9.1
,
Pullup/Pulldown Resistors
.
Specifies the operating I/O supply voltage for each signal
(3)
Device Overview
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