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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346C–JANUARY 2007–REVISED NOVEMBER 2007
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 5.3
Section 5.3
, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted):
Updated/Changed table note
from
"Measured under the following conditions..."
to
"Assumes the following
conditions..."
Deleted "V
I
= V
SS
to DV
DD33
without internal pullup resistor" from Input current [DC] (except I2C and PCI
capable pins) row
Updated/Changed I
OZ
V
O
= DV
DD33
or V
SS
; internal pull disabled MAX value
from
"
±
20
μ
A"
to
"
±
50
μ
A"
Updated/Changed I
OH
CLK_OUT0/PWM2/GPIO[84] MAX value
from
"8mA"
to
"-8 mA"
Updated/Changed I
OH
All other peripherals MAX value
from
"4mA"
to
"-4 mA"
Updated/Changed I
CDD
CVDD = 1.2V, DSP clock = 600 MHz supply current
from
"TBD"
to
"524 mA"
Updated/Changed I
CDD
CVDD = 1.2V, DSP clock = 500 MHz supply current
from
"TBD"
to
"460 mA"
Updated/Changed I
CDD
CVDD = 1.2V, DSP clock = 400 MHz supply current
from
"TBD"
to
"392 mA"
Updated/Changed I
CDD
CVDD = 1.05V, DSP clock = 400MHz supply current
from
"TBD"
to
"341 mA"
Updated/Changed I
DDD
3.3 V I/O DSP clock = 600 MHz supply current
from
"TBD"
to
"13 mA"
Updated/Changed I
DDD
3.3 V I/O DSP clock = 500 MHz supply current
from
"TBD"
to
"13 mA"
Updated/Changed I
DDD
3.3 V I/O DSP clock = 400 MHz supply current
from
"TBD"
to
"13 mA"
Updated/Changed I
DDD
1.8V I/O, CV
DD
= 1.2 V, DSP clock = 600 MHz supply current
from
"TBD"
to
"93
mA"
Updated/Changed I
DDD
1.8V I/O, CV
DD
= 1.2 V, DSP clock = 500 MHz supply current
from
"TBD"
to
"92
mA"
Updated/Changed I
DDD
1.8V I/O, CV
DD
= 1.2 V, DSP clock = 400 MHz supply current
from
"TBD"
to
"91
mA"
Updated/Changed I
DDD
1.8V I/O, CV
DD
= 1.05 V, DSP clock = 400 MHz supply current
from
"TBD"
to
"72
mA"
Section 6.5.2
, Warm Reset (RESET Pin):
Updated/Changed step 3
from
"The POR pin may now be deasserted"
to
"The RESET pin may now be
deasserted"
Updated/Changed step 3
from
"When the POR pin is deasserted"
to
"When the RESET pin is
deasserted"
Section 6.5.6
, Reset Priority:
Updated/Changed first paragraph
from
"The rest request priorities..."
to
"The reset request priorities..."
Section 6.6.1
, Clock Input Option 1:
Section 6.5.2
Section 6.5.6
Section 6.6.1
Deleted Frequency Stability row from
Table 6-13
Section 6.7.1
, PLL1 and PLL2:
Table 6-15
, PLLC1 Clock Frequency Ranges:
Added "-6 devices at 1.05-V CV
DD
" and "400 MHz" MAX value to SYSCLK1 (CLKDIV1 Domain) row
Section 6.7.1
Table
Updated/Changed PLL2_SYSCLK1 (to DDR2 PHY) MAX value
from
"333 MHz"
to
"266 MHz"
Updated/Changed PLLOUT MIN values
from
"400 MHz"
to
"300 MHz"
Section 6.8
, Interrupts:
Deleted "NMI" from "Also, the interrupt controller controls the generation of the CPU exception, NMI, and
emulation interrupts" sentence
Added "The NMI input to the C64x+ DSP interrupt controller is not connected internally; therefore, the
NMI interrupt is not available."
Section 6.9.3
, EMIFA Electrical Data/Timing
6-16
,
PLLC2
Clock
Frequency
Ranges:
Section 6.8
Section 6.9.3
Table 6-24
, Timing Requirements for Asynchronous Memory Cycles for EMIFA Module:
Added "NOM" column to represent nominal values
Updated/Changed t
su(EMDV-EMOEH)
MIN value
from
"TBD"
to
"5 ns"
Updated/Changed t
su(EMOEH-EMDIV)
MIN value
from
"TBD"
to
"0 ns"
Updated/Changed t
su(EMWAIT-EMOEH)
MIN value
from
"4E + TBD"
to
"4E + 5 ns"
Updated/Changed t
su(EMWAIT-EMWEH)
MIN value
from
"4E + TBD"
to
"4E + 5 ns"
Table 6-25
, Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module:
Added "NOM" column to represent nominal values
Added "When EW = 1, the EMIF will extend the strobe period up to 4,096 cycles..." table note
Deleted "EW = 1"
from
t
c(EMRCYCLE),
t
w(EMOEL),
t
c(EMWCYCLE), and
t
w(EMWEL)
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